249 lines
23 KiB
C
249 lines
23 KiB
C
/**
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* \file
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*
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* \brief Component description for CHIPID
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_CHIPID_COMPONENT_H_
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#define _SAME70_CHIPID_COMPONENT_H_
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#define _SAME70_CHIPID_COMPONENT_ /**< \deprecated Backward compatibility for ASF */
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/** \addtogroup SAME_SAME70 Chip Identifier
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* @{
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*/
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR CHIPID */
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/* ========================================================================== */
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#ifndef COMPONENT_TYPEDEF_STYLE
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#define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/
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#endif
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#define CHIPID_6417 /**< (CHIPID) Module ID */
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#define REV_CHIPID ZK /**< (CHIPID) Module revision */
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/* -------- CHIPID_CIDR : (CHIPID Offset: 0x00) (R/ 32) Chip ID Register -------- */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#if COMPONENT_TYPEDEF_STYLE == 'N'
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typedef union {
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struct {
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uint32_t VERSION:5; /**< bit: 0..4 Version of the Device */
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uint32_t EPROC:3; /**< bit: 5..7 Embedded Processor */
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uint32_t NVPSIZ:4; /**< bit: 8..11 Nonvolatile Program Memory Size */
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uint32_t NVPSIZ2:4; /**< bit: 12..15 Second Nonvolatile Program Memory Size */
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uint32_t SRAMSIZ:4; /**< bit: 16..19 Internal SRAM Size */
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uint32_t ARCH:8; /**< bit: 20..27 Architecture Identifier */
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uint32_t NVPTYP:3; /**< bit: 28..30 Nonvolatile Program Memory Type */
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uint32_t EXT:1; /**< bit: 31 Extension Flag */
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} bit; /**< Structure used for bit access */
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uint32_t reg; /**< Type used for register access */
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} CHIPID_CIDR_Type;
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#endif
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define CHIPID_CIDR_OFFSET (0x00) /**< (CHIPID_CIDR) Chip ID Register Offset */
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#define CHIPID_CIDR_VERSION_Pos 0 /**< (CHIPID_CIDR) Version of the Device Position */
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#define CHIPID_CIDR_VERSION_Msk (_U_(0x1F) << CHIPID_CIDR_VERSION_Pos) /**< (CHIPID_CIDR) Version of the Device Mask */
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#define CHIPID_CIDR_VERSION(value) (CHIPID_CIDR_VERSION_Msk & ((value) << CHIPID_CIDR_VERSION_Pos))
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#define CHIPID_CIDR_EPROC_Pos 5 /**< (CHIPID_CIDR) Embedded Processor Position */
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#define CHIPID_CIDR_EPROC_Msk (_U_(0x7) << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Embedded Processor Mask */
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#define CHIPID_CIDR_EPROC(value) (CHIPID_CIDR_EPROC_Msk & ((value) << CHIPID_CIDR_EPROC_Pos))
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#define CHIPID_CIDR_EPROC_SAMx7_Val _U_(0x0) /**< (CHIPID_CIDR) Cortex-M7 */
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#define CHIPID_CIDR_EPROC_ARM946ES_Val _U_(0x1) /**< (CHIPID_CIDR) ARM946ES */
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#define CHIPID_CIDR_EPROC_ARM7TDMI_Val _U_(0x2) /**< (CHIPID_CIDR) ARM7TDMI */
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#define CHIPID_CIDR_EPROC_CM3_Val _U_(0x3) /**< (CHIPID_CIDR) Cortex-M3 */
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#define CHIPID_CIDR_EPROC_ARM920T_Val _U_(0x4) /**< (CHIPID_CIDR) ARM920T */
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#define CHIPID_CIDR_EPROC_ARM926EJS_Val _U_(0x5) /**< (CHIPID_CIDR) ARM926EJS */
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#define CHIPID_CIDR_EPROC_CA5_Val _U_(0x6) /**< (CHIPID_CIDR) Cortex-A5 */
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#define CHIPID_CIDR_EPROC_CM4_Val _U_(0x7) /**< (CHIPID_CIDR) Cortex-M4 */
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#define CHIPID_CIDR_EPROC_SAMx7 (CHIPID_CIDR_EPROC_SAMx7_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M7 Position */
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#define CHIPID_CIDR_EPROC_ARM946ES (CHIPID_CIDR_EPROC_ARM946ES_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM946ES Position */
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#define CHIPID_CIDR_EPROC_ARM7TDMI (CHIPID_CIDR_EPROC_ARM7TDMI_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM7TDMI Position */
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#define CHIPID_CIDR_EPROC_CM3 (CHIPID_CIDR_EPROC_CM3_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M3 Position */
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#define CHIPID_CIDR_EPROC_ARM920T (CHIPID_CIDR_EPROC_ARM920T_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM920T Position */
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#define CHIPID_CIDR_EPROC_ARM926EJS (CHIPID_CIDR_EPROC_ARM926EJS_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM926EJS Position */
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#define CHIPID_CIDR_EPROC_CA5 (CHIPID_CIDR_EPROC_CA5_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-A5 Position */
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#define CHIPID_CIDR_EPROC_CM4 (CHIPID_CIDR_EPROC_CM4_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M4 Position */
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#define CHIPID_CIDR_NVPSIZ_Pos 8 /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Position */
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#define CHIPID_CIDR_NVPSIZ_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Mask */
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#define CHIPID_CIDR_NVPSIZ(value) (CHIPID_CIDR_NVPSIZ_Msk & ((value) << CHIPID_CIDR_NVPSIZ_Pos))
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#define CHIPID_CIDR_NVPSIZ_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */
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#define CHIPID_CIDR_NVPSIZ_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_160K_Val _U_(0x8) /**< (CHIPID_CIDR) 160 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */
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#define CHIPID_CIDR_NVPSIZ_NONE (CHIPID_CIDR_NVPSIZ_NONE_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) None Position */
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#define CHIPID_CIDR_NVPSIZ_8K (CHIPID_CIDR_NVPSIZ_8K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ_16K (CHIPID_CIDR_NVPSIZ_16K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ_32K (CHIPID_CIDR_NVPSIZ_32K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ_64K (CHIPID_CIDR_NVPSIZ_64K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ_128K (CHIPID_CIDR_NVPSIZ_128K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ_160K (CHIPID_CIDR_NVPSIZ_160K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ_256K (CHIPID_CIDR_NVPSIZ_256K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ_512K (CHIPID_CIDR_NVPSIZ_512K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ_1024K (CHIPID_CIDR_NVPSIZ_1024K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ_2048K (CHIPID_CIDR_NVPSIZ_2048K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ2_Pos 12 /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Position */
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#define CHIPID_CIDR_NVPSIZ2_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Mask */
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#define CHIPID_CIDR_NVPSIZ2(value) (CHIPID_CIDR_NVPSIZ2_Msk & ((value) << CHIPID_CIDR_NVPSIZ2_Pos))
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#define CHIPID_CIDR_NVPSIZ2_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */
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#define CHIPID_CIDR_NVPSIZ2_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */
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#define CHIPID_CIDR_NVPSIZ2_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */
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#define CHIPID_CIDR_NVPSIZ2_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */
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#define CHIPID_CIDR_NVPSIZ2_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */
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#define CHIPID_CIDR_NVPSIZ2_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */
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#define CHIPID_CIDR_NVPSIZ2_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */
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#define CHIPID_CIDR_NVPSIZ2_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */
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#define CHIPID_CIDR_NVPSIZ2_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */
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#define CHIPID_CIDR_NVPSIZ2_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */
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#define CHIPID_CIDR_NVPSIZ2_NONE (CHIPID_CIDR_NVPSIZ2_NONE_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) None Position */
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#define CHIPID_CIDR_NVPSIZ2_8K (CHIPID_CIDR_NVPSIZ2_8K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ2_16K (CHIPID_CIDR_NVPSIZ2_16K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ2_32K (CHIPID_CIDR_NVPSIZ2_32K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ2_64K (CHIPID_CIDR_NVPSIZ2_64K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ2_128K (CHIPID_CIDR_NVPSIZ2_128K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ2_256K (CHIPID_CIDR_NVPSIZ2_256K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ2_512K (CHIPID_CIDR_NVPSIZ2_512K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ2_1024K (CHIPID_CIDR_NVPSIZ2_1024K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */
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#define CHIPID_CIDR_NVPSIZ2_2048K (CHIPID_CIDR_NVPSIZ2_2048K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_Pos 16 /**< (CHIPID_CIDR) Internal SRAM Size Position */
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#define CHIPID_CIDR_SRAMSIZ_Msk (_U_(0xF) << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) Internal SRAM Size Mask */
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#define CHIPID_CIDR_SRAMSIZ(value) (CHIPID_CIDR_SRAMSIZ_Msk & ((value) << CHIPID_CIDR_SRAMSIZ_Pos))
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#define CHIPID_CIDR_SRAMSIZ_48K_Val _U_(0x0) /**< (CHIPID_CIDR) 48 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_192K_Val _U_(0x1) /**< (CHIPID_CIDR) 192 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_384K_Val _U_(0x2) /**< (CHIPID_CIDR) 384 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_6K_Val _U_(0x3) /**< (CHIPID_CIDR) 6 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_24K_Val _U_(0x4) /**< (CHIPID_CIDR) 24 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_4K_Val _U_(0x5) /**< (CHIPID_CIDR) 4 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_80K_Val _U_(0x6) /**< (CHIPID_CIDR) 80 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_160K_Val _U_(0x7) /**< (CHIPID_CIDR) 160 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_8K_Val _U_(0x8) /**< (CHIPID_CIDR) 8 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_16K_Val _U_(0x9) /**< (CHIPID_CIDR) 16 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_32K_Val _U_(0xA) /**< (CHIPID_CIDR) 32 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_64K_Val _U_(0xB) /**< (CHIPID_CIDR) 64 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_128K_Val _U_(0xC) /**< (CHIPID_CIDR) 128 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_256K_Val _U_(0xD) /**< (CHIPID_CIDR) 256 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_96K_Val _U_(0xE) /**< (CHIPID_CIDR) 96 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_512K_Val _U_(0xF) /**< (CHIPID_CIDR) 512 Kbytes */
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#define CHIPID_CIDR_SRAMSIZ_48K (CHIPID_CIDR_SRAMSIZ_48K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 48 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_192K (CHIPID_CIDR_SRAMSIZ_192K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 192 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_384K (CHIPID_CIDR_SRAMSIZ_384K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 384 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_6K (CHIPID_CIDR_SRAMSIZ_6K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 6 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_24K (CHIPID_CIDR_SRAMSIZ_24K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 24 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_4K (CHIPID_CIDR_SRAMSIZ_4K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 4 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_80K (CHIPID_CIDR_SRAMSIZ_80K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 80 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_160K (CHIPID_CIDR_SRAMSIZ_160K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_8K (CHIPID_CIDR_SRAMSIZ_8K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_16K (CHIPID_CIDR_SRAMSIZ_16K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_32K (CHIPID_CIDR_SRAMSIZ_32K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_64K (CHIPID_CIDR_SRAMSIZ_64K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_128K (CHIPID_CIDR_SRAMSIZ_128K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_256K (CHIPID_CIDR_SRAMSIZ_256K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_96K (CHIPID_CIDR_SRAMSIZ_96K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 96 Kbytes Position */
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#define CHIPID_CIDR_SRAMSIZ_512K (CHIPID_CIDR_SRAMSIZ_512K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */
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#define CHIPID_CIDR_ARCH_Pos 20 /**< (CHIPID_CIDR) Architecture Identifier Position */
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#define CHIPID_CIDR_ARCH_Msk (_U_(0xFF) << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) Architecture Identifier Mask */
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#define CHIPID_CIDR_ARCH(value) (CHIPID_CIDR_ARCH_Msk & ((value) << CHIPID_CIDR_ARCH_Pos))
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#define CHIPID_CIDR_ARCH_SAME70_Val _U_(0x10) /**< (CHIPID_CIDR) SAM E70 */
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#define CHIPID_CIDR_ARCH_SAMS70_Val _U_(0x11) /**< (CHIPID_CIDR) SAM S70 */
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#define CHIPID_CIDR_ARCH_SAMV71_Val _U_(0x12) /**< (CHIPID_CIDR) SAM V71 */
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#define CHIPID_CIDR_ARCH_SAMV70_Val _U_(0x13) /**< (CHIPID_CIDR) SAM V70 */
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#define CHIPID_CIDR_ARCH_SAME70 (CHIPID_CIDR_ARCH_SAME70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM E70 Position */
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#define CHIPID_CIDR_ARCH_SAMS70 (CHIPID_CIDR_ARCH_SAMS70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM S70 Position */
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#define CHIPID_CIDR_ARCH_SAMV71 (CHIPID_CIDR_ARCH_SAMV71_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V71 Position */
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#define CHIPID_CIDR_ARCH_SAMV70 (CHIPID_CIDR_ARCH_SAMV70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V70 Position */
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#define CHIPID_CIDR_NVPTYP_Pos 28 /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Position */
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#define CHIPID_CIDR_NVPTYP_Msk (_U_(0x7) << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Mask */
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#define CHIPID_CIDR_NVPTYP(value) (CHIPID_CIDR_NVPTYP_Msk & ((value) << CHIPID_CIDR_NVPTYP_Pos))
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#define CHIPID_CIDR_NVPTYP_ROM_Val _U_(0x0) /**< (CHIPID_CIDR) ROM */
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#define CHIPID_CIDR_NVPTYP_ROMLESS_Val _U_(0x1) /**< (CHIPID_CIDR) ROMless or on-chip Flash */
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#define CHIPID_CIDR_NVPTYP_FLASH_Val _U_(0x2) /**< (CHIPID_CIDR) Embedded Flash Memory */
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#define CHIPID_CIDR_NVPTYP_ROM_FLASH_Val _U_(0x3) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */
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#define CHIPID_CIDR_NVPTYP_SRAM_Val _U_(0x4) /**< (CHIPID_CIDR) SRAM emulating ROM */
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#define CHIPID_CIDR_NVPTYP_ROM (CHIPID_CIDR_NVPTYP_ROM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM Position */
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#define CHIPID_CIDR_NVPTYP_ROMLESS (CHIPID_CIDR_NVPTYP_ROMLESS_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROMless or on-chip Flash Position */
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#define CHIPID_CIDR_NVPTYP_FLASH (CHIPID_CIDR_NVPTYP_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Embedded Flash Memory Position */
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#define CHIPID_CIDR_NVPTYP_ROM_FLASH (CHIPID_CIDR_NVPTYP_ROM_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size Position */
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#define CHIPID_CIDR_NVPTYP_SRAM (CHIPID_CIDR_NVPTYP_SRAM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) SRAM emulating ROM Position */
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#define CHIPID_CIDR_EXT_Pos 31 /**< (CHIPID_CIDR) Extension Flag Position */
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#define CHIPID_CIDR_EXT_Msk (_U_(0x1) << CHIPID_CIDR_EXT_Pos) /**< (CHIPID_CIDR) Extension Flag Mask */
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#define CHIPID_CIDR_EXT CHIPID_CIDR_EXT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CHIPID_CIDR_EXT_Msk instead */
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#define CHIPID_CIDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (CHIPID_CIDR) Register MASK (Use CHIPID_CIDR_Msk instead) */
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#define CHIPID_CIDR_Msk _U_(0xFFFFFFFF) /**< (CHIPID_CIDR) Register Mask */
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/* -------- CHIPID_EXID : (CHIPID Offset: 0x04) (R/ 32) Chip ID Extension Register -------- */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#if COMPONENT_TYPEDEF_STYLE == 'N'
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typedef union {
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struct {
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uint32_t EXID:32; /**< bit: 0..31 Chip ID Extension */
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} bit; /**< Structure used for bit access */
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uint32_t reg; /**< Type used for register access */
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} CHIPID_EXID_Type;
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#endif
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define CHIPID_EXID_OFFSET (0x04) /**< (CHIPID_EXID) Chip ID Extension Register Offset */
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#define CHIPID_EXID_EXID_Pos 0 /**< (CHIPID_EXID) Chip ID Extension Position */
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#define CHIPID_EXID_EXID_Msk (_U_(0xFFFFFFFF) << CHIPID_EXID_EXID_Pos) /**< (CHIPID_EXID) Chip ID Extension Mask */
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#define CHIPID_EXID_EXID(value) (CHIPID_EXID_EXID_Msk & ((value) << CHIPID_EXID_EXID_Pos))
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#define CHIPID_EXID_MASK _U_(0xFFFFFFFF) /**< \deprecated (CHIPID_EXID) Register MASK (Use CHIPID_EXID_Msk instead) */
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#define CHIPID_EXID_Msk _U_(0xFFFFFFFF) /**< (CHIPID_EXID) Register Mask */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#if COMPONENT_TYPEDEF_STYLE == 'R'
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/** \brief CHIPID hardware registers */
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typedef struct {
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__I uint32_t CHIPID_CIDR; /**< (CHIPID Offset: 0x00) Chip ID Register */
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__I uint32_t CHIPID_EXID; /**< (CHIPID Offset: 0x04) Chip ID Extension Register */
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} Chipid;
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#elif COMPONENT_TYPEDEF_STYLE == 'N'
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/** \brief CHIPID hardware registers */
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typedef struct {
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__I CHIPID_CIDR_Type CHIPID_CIDR; /**< Offset: 0x00 (R/ 32) Chip ID Register */
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__I CHIPID_EXID_Type CHIPID_EXID; /**< Offset: 0x04 (R/ 32) Chip ID Extension Register */
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} Chipid;
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#else /* COMPONENT_TYPEDEF_STYLE */
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#error Unknown component typedef style
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#endif /* COMPONENT_TYPEDEF_STYLE */
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/** @} end of Chip Identifier */
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#endif /* _SAME70_CHIPID_COMPONENT_H_ */
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