97 lines
7.3 KiB
C
97 lines
7.3 KiB
C
/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2012, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following condition is met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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#ifndef _SAM3XA_USART2_INSTANCE_
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#define _SAM3XA_USART2_INSTANCE_
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/* ========== Register definition for USART2 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_USART2_CR (0x400A0000U) /**< \brief (USART2) Control Register */
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#define REG_USART2_MR (0x400A0004U) /**< \brief (USART2) Mode Register */
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#define REG_USART2_IER (0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */
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#define REG_USART2_IDR (0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */
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#define REG_USART2_IMR (0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */
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#define REG_USART2_CSR (0x400A0014U) /**< \brief (USART2) Channel Status Register */
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#define REG_USART2_RHR (0x400A0018U) /**< \brief (USART2) Receiver Holding Register */
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#define REG_USART2_THR (0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */
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#define REG_USART2_BRGR (0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */
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#define REG_USART2_RTOR (0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */
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#define REG_USART2_TTGR (0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */
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#define REG_USART2_FIDI (0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */
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#define REG_USART2_NER (0x400A0044U) /**< \brief (USART2) Number of Errors Register */
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#define REG_USART2_IF (0x400A004CU) /**< \brief (USART2) IrDA Filter Register */
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#define REG_USART2_MAN (0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
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#define REG_USART2_LINMR (0x400A0054U) /**< \brief (USART2) LIN Mode Register */
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#define REG_USART2_LINIR (0x400A0058U) /**< \brief (USART2) LIN Identifier Register */
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#define REG_USART2_WPMR (0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */
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#define REG_USART2_WPSR (0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */
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#define REG_USART2_RPR (0x400A0100U) /**< \brief (USART2) Receive Pointer Register */
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#define REG_USART2_RCR (0x400A0104U) /**< \brief (USART2) Receive Counter Register */
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#define REG_USART2_TPR (0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */
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#define REG_USART2_TCR (0x400A010CU) /**< \brief (USART2) Transmit Counter Register */
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#define REG_USART2_RNPR (0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */
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#define REG_USART2_RNCR (0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */
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#define REG_USART2_TNPR (0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */
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#define REG_USART2_TNCR (0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */
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#define REG_USART2_PTCR (0x400A0120U) /**< \brief (USART2) Transfer Control Register */
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#define REG_USART2_PTSR (0x400A0124U) /**< \brief (USART2) Transfer Status Register */
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#else
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#define REG_USART2_CR (*(WoReg*)0x400A0000U) /**< \brief (USART2) Control Register */
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#define REG_USART2_MR (*(RwReg*)0x400A0004U) /**< \brief (USART2) Mode Register */
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#define REG_USART2_IER (*(WoReg*)0x400A0008U) /**< \brief (USART2) Interrupt Enable Register */
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#define REG_USART2_IDR (*(WoReg*)0x400A000CU) /**< \brief (USART2) Interrupt Disable Register */
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#define REG_USART2_IMR (*(RoReg*)0x400A0010U) /**< \brief (USART2) Interrupt Mask Register */
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#define REG_USART2_CSR (*(RoReg*)0x400A0014U) /**< \brief (USART2) Channel Status Register */
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#define REG_USART2_RHR (*(RoReg*)0x400A0018U) /**< \brief (USART2) Receiver Holding Register */
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#define REG_USART2_THR (*(WoReg*)0x400A001CU) /**< \brief (USART2) Transmitter Holding Register */
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#define REG_USART2_BRGR (*(RwReg*)0x400A0020U) /**< \brief (USART2) Baud Rate Generator Register */
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#define REG_USART2_RTOR (*(RwReg*)0x400A0024U) /**< \brief (USART2) Receiver Time-out Register */
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#define REG_USART2_TTGR (*(RwReg*)0x400A0028U) /**< \brief (USART2) Transmitter Timeguard Register */
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#define REG_USART2_FIDI (*(RwReg*)0x400A0040U) /**< \brief (USART2) FI DI Ratio Register */
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#define REG_USART2_NER (*(RoReg*)0x400A0044U) /**< \brief (USART2) Number of Errors Register */
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#define REG_USART2_IF (*(RwReg*)0x400A004CU) /**< \brief (USART2) IrDA Filter Register */
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#define REG_USART2_MAN (*(RwReg*)0x400A0050U) /**< \brief (USART2) Manchester Encoder Decoder Register */
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#define REG_USART2_LINMR (*(RwReg*)0x400A0054U) /**< \brief (USART2) LIN Mode Register */
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#define REG_USART2_LINIR (*(RwReg*)0x400A0058U) /**< \brief (USART2) LIN Identifier Register */
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#define REG_USART2_WPMR (*(RwReg*)0x400A00E4U) /**< \brief (USART2) Write Protect Mode Register */
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#define REG_USART2_WPSR (*(RoReg*)0x400A00E8U) /**< \brief (USART2) Write Protect Status Register */
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#define REG_USART2_RPR (*(RwReg*)0x400A0100U) /**< \brief (USART2) Receive Pointer Register */
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#define REG_USART2_RCR (*(RwReg*)0x400A0104U) /**< \brief (USART2) Receive Counter Register */
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#define REG_USART2_TPR (*(RwReg*)0x400A0108U) /**< \brief (USART2) Transmit Pointer Register */
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#define REG_USART2_TCR (*(RwReg*)0x400A010CU) /**< \brief (USART2) Transmit Counter Register */
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#define REG_USART2_RNPR (*(RwReg*)0x400A0110U) /**< \brief (USART2) Receive Next Pointer Register */
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#define REG_USART2_RNCR (*(RwReg*)0x400A0114U) /**< \brief (USART2) Receive Next Counter Register */
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#define REG_USART2_TNPR (*(RwReg*)0x400A0118U) /**< \brief (USART2) Transmit Next Pointer Register */
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#define REG_USART2_TNCR (*(RwReg*)0x400A011CU) /**< \brief (USART2) Transmit Next Counter Register */
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#define REG_USART2_PTCR (*(WoReg*)0x400A0120U) /**< \brief (USART2) Transfer Control Register */
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#define REG_USART2_PTSR (*(RoReg*)0x400A0124U) /**< \brief (USART2) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3XA_USART2_INSTANCE_ */
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