600 lines
19 KiB
C
600 lines
19 KiB
C
/**
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******************************************************************************
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* @file stm32f0xx_ll_rcc.c
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* @author MCD Application Team
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* @brief RCC LL module driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx_ll_rcc.h"
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#ifdef USE_FULL_ASSERT
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#include "stm32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif /* USE_FULL_ASSERT */
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/** @addtogroup STM32F0xx_LL_Driver
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* @{
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*/
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#if defined(RCC)
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/** @defgroup RCC_LL RCC
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup RCC_LL_Private_Macros
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* @{
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*/
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#if defined(RCC_CFGR3_USART2SW) && defined(RCC_CFGR3_USART3SW)
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#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
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|| ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
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|| ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
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#elif defined(RCC_CFGR3_USART2SW) && !defined(RCC_CFGR3_USART3SW)
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#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
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|| ((__VALUE__) == LL_RCC_USART2_CLKSOURCE))
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#elif defined(RCC_CFGR3_USART3SW) && !defined(RCC_CFGR3_USART2SW)
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#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
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|| ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
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#else
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#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE))
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#endif /* RCC_CFGR3_USART2SW && RCC_CFGR3_USART3SW */
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#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_I2C1_CLKSOURCE)
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#if defined(USB)
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#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
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#endif /* USB */
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#if defined(CEC)
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#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
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#endif /* CEC */
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/** @defgroup RCC_LL_Private_Functions RCC Private functions
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* @{
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*/
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uint32_t RCC_GetSystemClockFreq(void);
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uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
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uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
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uint32_t RCC_PLL_GetFreqDomain_SYS(void);
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup RCC_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup RCC_LL_EF_Init
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* @{
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*/
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/**
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* @brief Reset the RCC clock configuration to the default reset state.
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* @note The default reset state of the clock configuration is given below:
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* - HSI ON and used as system clock source
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* - HSE and PLL OFF
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* - AHB and APB1 prescaler set to 1.
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* - CSS, MCO OFF
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* - All interrupts disabled
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* @note This function doesn't modify the configuration of the
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* - Peripheral clocks
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* - LSI, LSE and RTC clocks
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: RCC registers are de-initialized
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* - ERROR: not applicable
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*/
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ErrorStatus LL_RCC_DeInit(void)
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{
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uint32_t vl_mask = 0U;
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/* Set HSION bit */
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LL_RCC_HSI_Enable();
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/* Set HSITRIM bits to the reset value*/
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LL_RCC_HSI_SetCalibTrimming(0x10U);
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/* Reset SW, HPRE, PPRE and MCOSEL bits */
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vl_mask = 0xFFFFFFFFU;
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CLEAR_BIT(vl_mask, (RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCOSEL));
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LL_RCC_WriteReg(CFGR, vl_mask);
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/* Reset HSEON, CSSON, PLLON bits */
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vl_mask = 0xFFFFFFFFU;
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CLEAR_BIT(vl_mask, (RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON));
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LL_RCC_WriteReg(CR, vl_mask);
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/* Reset HSEBYP bit */
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LL_RCC_HSE_DisableBypass();
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/* Reset CFGR register */
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LL_RCC_WriteReg(CFGR, 0x00000000U);
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#if defined(RCC_HSI48_SUPPORT)
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/* Reset CR2 register */
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LL_RCC_WriteReg(CR2, 0x00000000U);
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/* Disable HSI48 */
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LL_RCC_HSI48_Disable();
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#endif /*RCC_HSI48_SUPPORT*/
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/* Set HSI14TRIM/HSI14ON/HSI14DIS bits to the reset value*/
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LL_RCC_HSI14_SetCalibTrimming(0x10U);
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LL_RCC_HSI14_Disable();
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LL_RCC_HSI14_EnableADCControl();
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/* Reset CFGR2 register */
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LL_RCC_WriteReg(CFGR2, 0x00000000U);
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/* Reset CFGR3 register */
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LL_RCC_WriteReg(CFGR3, 0x00000000U);
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/* Clear pending flags */
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#if defined(RCC_HSI48_SUPPORT)
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vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_HSI48RDYC | LL_RCC_CIR_CSSC);
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#else
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vl_mask = (LL_RCC_CIR_LSIRDYC | LL_RCC_CIR_LSERDYC | LL_RCC_CIR_HSIRDYC | LL_RCC_CIR_HSERDYC | LL_RCC_CIR_PLLRDYC | LL_RCC_CIR_HSI14RDYC | LL_RCC_CIR_CSSC);
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#endif /* RCC_HSI48_SUPPORT */
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SET_BIT(RCC->CIR, vl_mask);
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/* Disable all interrupts */
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LL_RCC_WriteReg(CIR, 0x00000000U);
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return SUCCESS;
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}
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/**
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* @}
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*/
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/** @addtogroup RCC_LL_EF_Get_Freq
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* @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
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* and different peripheral clocks available on the device.
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* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
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* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
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* @note If SYSCLK source is PLL, function returns values based on
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* HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
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* @note (**) HSI_VALUE is a defined constant but the real value may vary
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* depending on the variations in voltage and temperature.
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* @note (***) HSE_VALUE is a defined constant, user has to ensure that
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* HSE_VALUE is same as the real frequency of the crystal used.
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* Otherwise, this function may have wrong result.
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* @note The result of this function could be incorrect when using fractional
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* value for HSE crystal.
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* @note This function can be used by the user application to compute the
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* baud-rate for the communication peripherals or configure other parameters.
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* @{
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*/
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/**
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* @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks
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* @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function
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* must be called to update structure fields. Otherwise, any
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* configuration based on this function will be incorrect.
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* @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
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* @retval None
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*/
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void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
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{
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/* Get SYSCLK frequency */
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RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
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/* HCLK clock frequency */
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RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
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/* PCLK1 clock frequency */
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RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
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}
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/**
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* @brief Return USARTx clock frequency
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* @param USARTxSource This parameter can be one of the following values:
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* @arg @ref LL_RCC_USART1_CLKSOURCE
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* @arg @ref LL_RCC_USART2_CLKSOURCE (*)
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* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
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*
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* (*) value not defined in all devices.
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* @retval USART clock frequency (in Hz)
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* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
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*/
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uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
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{
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uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* Check parameter */
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assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
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#if defined(RCC_CFGR3_USART1SW)
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if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
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{
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/* USART1CLK clock frequency */
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switch (LL_RCC_GetUSARTClockSource(USARTxSource))
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{
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case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
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usart_frequency = RCC_GetSystemClockFreq();
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break;
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case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */
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if (LL_RCC_HSI_IsReady())
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{
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usart_frequency = HSI_VALUE;
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}
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break;
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case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */
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if (LL_RCC_LSE_IsReady())
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{
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usart_frequency = LSE_VALUE;
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}
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break;
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case LL_RCC_USART1_CLKSOURCE_PCLK1: /* USART1 Clock is PCLK1 */
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default:
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usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
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break;
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}
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}
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#endif /* RCC_CFGR3_USART1SW */
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#if defined(RCC_CFGR3_USART2SW)
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if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
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{
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/* USART2CLK clock frequency */
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switch (LL_RCC_GetUSARTClockSource(USARTxSource))
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{
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case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
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usart_frequency = RCC_GetSystemClockFreq();
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break;
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case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */
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if (LL_RCC_HSI_IsReady())
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{
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usart_frequency = HSI_VALUE;
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}
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break;
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case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */
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if (LL_RCC_LSE_IsReady())
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{
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usart_frequency = LSE_VALUE;
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}
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break;
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case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */
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default:
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usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
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break;
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}
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}
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#endif /* RCC_CFGR3_USART2SW */
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#if defined(RCC_CFGR3_USART3SW)
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if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
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{
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/* USART3CLK clock frequency */
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switch (LL_RCC_GetUSARTClockSource(USARTxSource))
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{
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case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
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usart_frequency = RCC_GetSystemClockFreq();
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break;
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case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */
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if (LL_RCC_HSI_IsReady())
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{
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usart_frequency = HSI_VALUE;
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}
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break;
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case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */
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if (LL_RCC_LSE_IsReady())
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{
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usart_frequency = LSE_VALUE;
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}
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break;
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case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */
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default:
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usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
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break;
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}
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}
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#endif /* RCC_CFGR3_USART3SW */
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return usart_frequency;
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}
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/**
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* @brief Return I2Cx clock frequency
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* @param I2CxSource This parameter can be one of the following values:
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* @arg @ref LL_RCC_I2C1_CLKSOURCE
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* @retval I2C clock frequency (in Hz)
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* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
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*/
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uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
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{
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uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* Check parameter */
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assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
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/* I2C1 CLK clock frequency */
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if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
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{
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switch (LL_RCC_GetI2CClockSource(I2CxSource))
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{
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case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
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i2c_frequency = RCC_GetSystemClockFreq();
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break;
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case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */
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default:
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if (LL_RCC_HSI_IsReady())
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{
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i2c_frequency = HSI_VALUE;
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}
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break;
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}
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}
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return i2c_frequency;
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}
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#if defined(USB)
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/**
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* @brief Return USBx clock frequency
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* @param USBxSource This parameter can be one of the following values:
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* @arg @ref LL_RCC_USB_CLKSOURCE
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* @retval USB clock frequency (in Hz)
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* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
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* @arg @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
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*/
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uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
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{
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uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* Check parameter */
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assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
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/* USBCLK clock frequency */
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switch (LL_RCC_GetUSBClockSource(USBxSource))
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{
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case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
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if (LL_RCC_PLL_IsReady())
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{
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usb_frequency = RCC_PLL_GetFreqDomain_SYS();
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}
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break;
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#if defined(RCC_CFGR3_USBSW_HSI48)
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case LL_RCC_USB_CLKSOURCE_HSI48: /* HSI48 clock used as USB clock source */
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default:
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if (LL_RCC_HSI48_IsReady())
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{
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usb_frequency = HSI48_VALUE;
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}
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break;
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#else
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case LL_RCC_USB_CLKSOURCE_NONE: /* No clock used as USB clock source */
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default:
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usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
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break;
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#endif /* RCC_CFGR3_USBSW_HSI48 */
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}
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return usb_frequency;
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}
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#endif /* USB */
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#if defined(CEC)
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/**
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* @brief Return CECx clock frequency
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* @param CECxSource This parameter can be one of the following values:
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* @arg @ref LL_RCC_CEC_CLKSOURCE
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* @retval CEC clock frequency (in Hz)
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* @arg @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (HSI or LSE) are not ready
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*/
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uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
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{
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uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
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/* Check parameter */
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assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
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/* CECCLK clock frequency */
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switch (LL_RCC_GetCECClockSource(CECxSource))
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{
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case LL_RCC_CEC_CLKSOURCE_HSI_DIV244: /* HSI / 244 clock used as CEC clock source */
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if (LL_RCC_HSI_IsReady())
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{
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cec_frequency = HSI_VALUE / 244U;
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}
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break;
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case LL_RCC_CEC_CLKSOURCE_LSE: /* LSE clock used as CEC clock source */
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default:
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if (LL_RCC_LSE_IsReady())
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{
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cec_frequency = LSE_VALUE;
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}
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break;
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}
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return cec_frequency;
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}
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#endif /* CEC */
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|
/**
|
|
* @}
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|
*/
|
|
|
|
/**
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|
* @}
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|
*/
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|
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/** @addtogroup RCC_LL_Private_Functions
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|
* @{
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|
*/
|
|
|
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/**
|
|
* @brief Return SYSTEM clock frequency
|
|
* @retval SYSTEM clock frequency (in Hz)
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|
*/
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|
uint32_t RCC_GetSystemClockFreq(void)
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|
{
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|
uint32_t frequency = 0U;
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
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|
switch (LL_RCC_GetSysClkSource())
|
|
{
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|
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
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|
frequency = HSI_VALUE;
|
|
break;
|
|
|
|
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
|
|
frequency = HSE_VALUE;
|
|
break;
|
|
|
|
case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
|
|
frequency = RCC_PLL_GetFreqDomain_SYS();
|
|
break;
|
|
|
|
#if defined(RCC_HSI48_SUPPORT)
|
|
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI48:/* HSI48 used as system clock source */
|
|
frequency = HSI48_VALUE;
|
|
break;
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
|
|
default:
|
|
frequency = HSI_VALUE;
|
|
break;
|
|
}
|
|
|
|
return frequency;
|
|
}
|
|
|
|
/**
|
|
* @brief Return HCLK clock frequency
|
|
* @param SYSCLK_Frequency SYSCLK clock frequency
|
|
* @retval HCLK clock frequency (in Hz)
|
|
*/
|
|
uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
|
|
{
|
|
/* HCLK clock frequency */
|
|
return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
|
|
}
|
|
|
|
/**
|
|
* @brief Return PCLK1 clock frequency
|
|
* @param HCLK_Frequency HCLK clock frequency
|
|
* @retval PCLK1 clock frequency (in Hz)
|
|
*/
|
|
uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
|
|
{
|
|
/* PCLK1 clock frequency */
|
|
return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
|
|
}
|
|
/**
|
|
* @brief Return PLL clock frequency used for system domain
|
|
* @retval PLL clock frequency (in Hz)
|
|
*/
|
|
uint32_t RCC_PLL_GetFreqDomain_SYS(void)
|
|
{
|
|
uint32_t pllinputfreq = 0U, pllsource = 0U;
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL divider) * PLL Multiplicator */
|
|
|
|
/* Get PLL source */
|
|
pllsource = LL_RCC_PLL_GetMainSource();
|
|
|
|
switch (pllsource)
|
|
{
|
|
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
|
case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllinputfreq = HSI_VALUE;
|
|
#else
|
|
case LL_RCC_PLLSOURCE_HSI_DIV_2: /* HSI used as PLL clock source */
|
|
pllinputfreq = HSI_VALUE / 2U;
|
|
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
|
|
break;
|
|
|
|
#if defined(RCC_HSI48_SUPPORT)
|
|
case LL_RCC_PLLSOURCE_HSI48: /* HSI48 used as PLL clock source */
|
|
pllinputfreq = HSI48_VALUE;
|
|
break;
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
|
|
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllinputfreq = HSE_VALUE;
|
|
break;
|
|
|
|
default:
|
|
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
|
pllinputfreq = HSI_VALUE;
|
|
#else
|
|
pllinputfreq = HSI_VALUE / 2U;
|
|
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
|
|
break;
|
|
}
|
|
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
|
|
return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetMultiplicator(), LL_RCC_PLL_GetPrediv());
|
|
#else
|
|
return __LL_RCC_CALC_PLLCLK_FREQ((pllinputfreq / (LL_RCC_PLL_GetPrediv() + 1U)), LL_RCC_PLL_GetMultiplicator());
|
|
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
|
|
}
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* defined(RCC) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|