234 lines
8.8 KiB
C
234 lines
8.8 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_hal_spi_ex.c
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief Extended SPI HAL module driver.
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*
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* This file provides firmware functions to manage the following
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* functionalities SPI extension peripheral:
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* + Extended Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @addtogroup SPI
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* @{
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*/
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#ifdef HAL_SPI_MODULE_ENABLED
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/** @defgroup SPI_Private_Variables SPI Private Variables
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* @{
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*/
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#if (USE_SPI_CRC != 0U)
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/* Variable used to determine if device is impacted by implementation of workaround
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related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
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- STM32F101CDE/STM32F103CDE
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- Revision ID : Z
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- SPI2
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- In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
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the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
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+ If the value is 0, the complete data transfer is successful.
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+ Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
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If CRCERR is found reset, the complete data transfer is considered successful.
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*/
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uint8_t uCRCErrorWorkaroundCheck = 0U;
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#endif /* USE_SPI_CRC */
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/**
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* @}
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @addtogroup SPI_Exported_Functions
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* @{
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*/
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/** @addtogroup SPI_Exported_Functions_Group1
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*
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* @{
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*/
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/**
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* @brief Initializes the SPI according to the specified parameters
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* in the SPI_InitTypeDef and create the associated handle.
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* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
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* the configuration information for SPI module.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
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{
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/* Check the SPI handle allocation */
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if(hspi == NULL)
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{
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return HAL_ERROR;
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}
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/* Check the parameters */
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assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
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assert_param(IS_SPI_MODE(hspi->Init.Mode));
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assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
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assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
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assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
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assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
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assert_param(IS_SPI_NSS(hspi->Init.NSS));
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assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
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assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
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#if (USE_SPI_CRC != 0U)
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assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
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if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
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{
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assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
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}
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#else
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hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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#endif /* USE_SPI_CRC */
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if(hspi->State == HAL_SPI_STATE_RESET)
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{
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/* Init the low level hardware : GPIO, CLOCK, NVIC... */
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HAL_SPI_MspInit(hspi);
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}
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hspi->State = HAL_SPI_STATE_BUSY;
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/* Disble the selected SPI peripheral */
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__HAL_SPI_DISABLE(hspi);
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/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
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/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
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Communication speed, First bit and CRC calculation state */
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WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
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hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
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hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) );
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/* Configure : NSS management */
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WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode));
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/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
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/* Configure : CRC Polynomial */
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WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
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#if defined(SPI_I2SCFGR_I2SMOD)
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/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
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CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
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#endif /* SPI_I2SCFGR_I2SMOD */
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#if (USE_SPI_CRC != 0U)
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#if defined (STM32F101xE) || defined (STM32F103xE)
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/* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
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CRC errors wrongly detected */
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/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
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Revision ID information is only available in Debug mode, so Workaround could not be implemented
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to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
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So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
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uCRCErrorWorkaroundCheck = 0U;
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#else
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uCRCErrorWorkaroundCheck = 0U;
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#endif /* STM32F101xE || STM32F103xE */
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#endif /* USE_SPI_CRC */
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hspi->ErrorCode = HAL_SPI_ERROR_NONE;
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hspi->State = HAL_SPI_STATE_READY;
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return HAL_OK;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @addtogroup SPI_Private_Functions
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* @{
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*/
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#if (USE_SPI_CRC != 0U)
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/**
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* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
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* according to SPI instance, Device type, and revision ID.
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* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
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* the configuration information for SPI module.
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* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
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*/
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uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi)
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{
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#if defined(STM32F101xE) || defined(STM32F103xE)
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/* Check how to handle this CRC error (workaround to be applied or not) */
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/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
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if((uCRCErrorWorkaroundCheck != 0U) && (hspi->Instance == SPI2))
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{
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if(hspi->Instance->RXCRCR == 0U)
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{
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return (SPI_INVALID_CRC_ERROR);
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}
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}
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return (SPI_VALID_CRC_ERROR);
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#else
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/* Prevent unused argument(s) compilation warning */
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UNUSED(hspi);
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return (SPI_VALID_CRC_ERROR);
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#endif
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}
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#endif /* USE_SPI_CRC */
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/**
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* @}
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*/
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#endif /* HAL_SPI_MODULE_ENABLED */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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