882 lines
32 KiB
C
882 lines
32 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_hal_rcc_ex.c
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief Extended RCC HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities RCC extension peripheral:
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* + Extended Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/** @defgroup RCCEx RCCEx
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* @brief RCC Extension HAL module driver.
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* @{
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*/
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
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* @{
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*/
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
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* @{
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*/
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/**
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* @}
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*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
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* @{
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*/
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/** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
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* @brief Extended Peripheral Control functions
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*
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@verbatim
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===============================================================================
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##### Extended Peripheral Control functions #####
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===============================================================================
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[..]
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This subsection provides a set of functions allowing to control the RCC Clocks
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frequencies.
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[..]
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(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
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select the RTC clock source; in this case the Backup domain will be reset in
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order to modify the RTC Clock source, as consequence RTC registers (including
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the backup registers) are set to their reset values.
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@endverbatim
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* @{
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*/
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/**
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* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
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* RCC_PeriphCLKInitTypeDef.
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* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
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* contains the configuration information for the Extended Peripherals clocks(RTC clock).
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*
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* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
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* the RTC clock source; in this case the Backup domain will be reset in
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* order to modify the RTC Clock source, as consequence RTC registers (including
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* the backup registers) are set to their reset values.
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*
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* @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
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* one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
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* manually disable it.
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*
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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uint32_t tickstart = 0U, temp_reg = 0U;
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#if defined(STM32F105xC) || defined(STM32F107xC)
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uint32_t pllactive = 0U;
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#endif /* STM32F105xC || STM32F107xC */
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/* Check the parameters */
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
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/*------------------------------- RTC/LCD Configuration ------------------------*/
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if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
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{
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/* check for RTC Parameters used to output RTCCLK */
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assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
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FlagStatus pwrclkchanged = RESET;
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/* As soon as function is called to change RTC clock source, activation of the
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power domain is done. */
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/* Requires to enable write access to Backup Domain of necessary */
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if(__HAL_RCC_PWR_IS_CLK_DISABLED())
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{
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__HAL_RCC_PWR_CLK_ENABLE();
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pwrclkchanged = SET;
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}
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if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
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{
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/* Enable write access to Backup domain */
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SET_BIT(PWR->CR, PWR_CR_DBP);
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/* Wait for Backup domain Write protection disable */
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tickstart = HAL_GetTick();
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while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
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{
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if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
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temp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
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if((temp_reg != 0x00000000U) && (temp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
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{
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/* Store the content of BDCR register before the reset of Backup Domain */
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temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
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/* RTC Clock selection can be changed only if the Backup Domain is reset */
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__HAL_RCC_BACKUPRESET_FORCE();
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__HAL_RCC_BACKUPRESET_RELEASE();
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/* Restore the Content of BDCR register */
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RCC->BDCR = temp_reg;
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/* Wait for LSERDY if LSE was enabled */
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if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSEON))
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{
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till LSE is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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{
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if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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}
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__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
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/* Require to disable power clock if necessary */
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if(pwrclkchanged == SET)
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{
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__HAL_RCC_PWR_CLK_DISABLE();
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}
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}
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/*------------------------------ ADC clock Configuration ------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
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{
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/* Check the parameters */
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assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
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/* Configure the ADC clock source */
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__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
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}
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#if defined(STM32F105xC) || defined(STM32F107xC)
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/*------------------------------ I2S2 Configuration ------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
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{
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/* Check the parameters */
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assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
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/* Configure the I2S2 clock source */
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__HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
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}
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/*------------------------------ I2S3 Configuration ------------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
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{
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/* Check the parameters */
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assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
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/* Configure the I2S3 clock source */
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__HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
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}
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/*------------------------------ PLL I2S Configuration ----------------------*/
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/* Check that PLLI2S need to be enabled */
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if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
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{
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/* Update flag to indicate that PLL I2S should be active */
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pllactive = 1;
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}
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/* Check if PLL I2S need to be enabled */
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if (pllactive == 1)
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{
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/* Enable PLL I2S only if not active */
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if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
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{
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/* Check the parameters */
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assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
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assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
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/* Prediv2 can be written only when the PLL2 is disabled. */
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/* Return an error only if new value is different from the programmed value */
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if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
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(__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
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{
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return HAL_ERROR;
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}
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/* Configure the HSE prediv2 factor --------------------------------*/
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__HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
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/* Configure the main PLLI2S multiplication factors. */
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__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
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/* Enable the main PLLI2S. */
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__HAL_RCC_PLLI2S_ENABLE();
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/* Get Start Tick*/
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tickstart = HAL_GetTick();
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/* Wait till PLLI2S is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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else
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{
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/* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
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if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
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{
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return HAL_ERROR;
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}
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}
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}
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#endif /* STM32F105xC || STM32F107xC */
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#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
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|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
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|| defined(STM32F105xC) || defined(STM32F107xC)
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/*------------------------------ USB clock Configuration ------------------*/
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if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
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{
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/* Check the parameters */
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assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
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/* Configure the USB clock source */
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__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
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}
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#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
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return HAL_OK;
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}
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/**
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* @brief Get the PeriphClkInit according to the internal
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* RCC configuration registers.
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* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
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* returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
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* @retval None
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*/
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void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
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{
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uint32_t srcclk = 0U;
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/* Set all possible values for the extended clock type parameter------------*/
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PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
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/* Get the RTC configuration -----------------------------------------------*/
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srcclk = __HAL_RCC_GET_RTC_SOURCE();
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/* Source clock is LSE or LSI*/
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PeriphClkInit->RTCClockSelection = srcclk;
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/* Get the ADC clock configuration -----------------------------------------*/
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
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PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
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#if defined(STM32F105xC) || defined(STM32F107xC)
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/* Get the I2S2 clock configuration -----------------------------------------*/
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
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PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
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/* Get the I2S3 clock configuration -----------------------------------------*/
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
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PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
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#endif /* STM32F105xC || STM32F107xC */
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#if defined(STM32F103xE) || defined(STM32F103xG)
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/* Get the I2S2 clock configuration -----------------------------------------*/
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
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PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
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/* Get the I2S3 clock configuration -----------------------------------------*/
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
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PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
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#endif /* STM32F103xE || STM32F103xG */
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#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
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|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
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|| defined(STM32F105xC) || defined(STM32F107xC)
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/* Get the USB clock configuration -----------------------------------------*/
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PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
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PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
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#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
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}
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/**
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* @brief Returns the peripheral clock frequency
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* @note Returns 0 if peripheral clock is unknown
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* @param PeriphClk Peripheral clock identifier
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* This parameter can be one of the following values:
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* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
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* @arg @ref RCC_PERIPHCLK_ADC ADC peripheral clock
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@if STM32F103xE
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* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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@endif
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@if STM32F103xG
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* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
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@endif
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@if STM32F105xC
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* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
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@endif
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@if STM32F107xC
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* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S3 I2S3 peripheral clock
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* @arg @ref RCC_PERIPHCLK_I2S2 I2S2 peripheral clock
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* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
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@endif
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@if STM32F102xx
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* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
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@endif
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@if STM32F103xx
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* @arg @ref RCC_PERIPHCLK_USB USB peripheral clock
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@endif
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* @retval Frequency in Hz (0: means that no available frequency for the peripheral)
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*/
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uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
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{
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#if defined(STM32F105xC) || defined(STM32F107xC)
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const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
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const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
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uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
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uint32_t pll2mul = 0U, pll3mul = 0U, prediv2 = 0U;
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#endif /* STM32F105xC || STM32F107xC */
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#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || \
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defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
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const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
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const uint8_t aPredivFactorTable[2] = {1, 2};
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uint32_t prediv1 = 0U, pllclk = 0U, pllmul = 0U;
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#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
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uint32_t temp_reg = 0U, frequency = 0U;
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/* Check the parameters */
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assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
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switch (PeriphClk)
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{
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#if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
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|| defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
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|| defined(STM32F105xC) || defined(STM32F107xC)
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case RCC_PERIPHCLK_USB:
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{
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/* Get RCC configuration ------------------------------------------------------*/
|
|
temp_reg = RCC->CFGR;
|
|
|
|
/* Check if PLL is enabled */
|
|
if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(temp_reg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
{
|
|
#if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
|
|
|| defined(STM32F100xE)
|
|
prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
|
|
#else
|
|
prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
#endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
|
|
|
|
#if defined(STM32F105xC) || defined(STM32F107xC)
|
|
if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
|
|
{
|
|
/* PLL2 selected as Prediv1 source */
|
|
/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
|
|
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
|
|
pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
|
|
pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
|
|
}
|
|
else
|
|
{
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
|
|
}
|
|
|
|
/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
|
|
/* In this case need to divide pllclk by 2 */
|
|
if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
|
|
{
|
|
pllclk = pllclk / 2;
|
|
}
|
|
#else
|
|
if ((temp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
{
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
|
|
}
|
|
#endif /* STM32F105xC || STM32F107xC */
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
}
|
|
|
|
/* Calcul of the USB frequency*/
|
|
#if defined(STM32F105xC) || defined(STM32F107xC)
|
|
/* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
|
|
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL_DIV2)
|
|
{
|
|
/* Prescaler of 2 selected for USB */
|
|
frequency = pllclk;
|
|
}
|
|
else
|
|
{
|
|
/* Prescaler of 3 selected for USB */
|
|
frequency = (2 * pllclk) / 3;
|
|
}
|
|
#else
|
|
/* USBCLK = PLLCLK / USB prescaler */
|
|
if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBCLKSOURCE_PLL)
|
|
{
|
|
/* No prescaler selected for USB */
|
|
frequency = pllclk;
|
|
}
|
|
else
|
|
{
|
|
/* Prescaler of 1.5 selected for USB */
|
|
frequency = (pllclk * 2) / 3;
|
|
}
|
|
#endif
|
|
}
|
|
break;
|
|
}
|
|
#endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
|
#if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
|
|
case RCC_PERIPHCLK_I2S2:
|
|
{
|
|
#if defined(STM32F103xE) || defined(STM32F103xG)
|
|
/* SYSCLK used as source clock for I2S2 */
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
#else
|
|
if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
|
|
{
|
|
/* SYSCLK used as source clock for I2S2 */
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
else
|
|
{
|
|
/* Check if PLLI2S is enabled */
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
|
|
{
|
|
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
|
|
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
|
|
pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
|
|
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
|
|
}
|
|
}
|
|
#endif /* STM32F103xE || STM32F103xG */
|
|
break;
|
|
}
|
|
case RCC_PERIPHCLK_I2S3:
|
|
{
|
|
#if defined(STM32F103xE) || defined(STM32F103xG)
|
|
/* SYSCLK used as source clock for I2S3 */
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
#else
|
|
if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
|
|
{
|
|
/* SYSCLK used as source clock for I2S3 */
|
|
frequency = HAL_RCC_GetSysClockFreq();
|
|
}
|
|
else
|
|
{
|
|
/* Check if PLLI2S is enabled */
|
|
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
|
|
{
|
|
/* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
|
|
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
|
|
pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> RCC_CFGR2_PLL3MUL_Pos) + 2;
|
|
frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
|
|
}
|
|
}
|
|
#endif /* STM32F103xE || STM32F103xG */
|
|
break;
|
|
}
|
|
#endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
|
|
case RCC_PERIPHCLK_RTC:
|
|
{
|
|
/* Get RCC BDCR configuration ------------------------------------------------------*/
|
|
temp_reg = RCC->BDCR;
|
|
|
|
/* Check if LSE is ready if RTC clock selection is LSE */
|
|
if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY)))
|
|
{
|
|
frequency = LSE_VALUE;
|
|
}
|
|
/* Check if LSI is ready if RTC clock selection is LSI */
|
|
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
|
|
{
|
|
frequency = LSI_VALUE;
|
|
}
|
|
else if (((temp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
|
|
{
|
|
frequency = HSE_VALUE / 128U;
|
|
}
|
|
/* Clock not enabled for RTC*/
|
|
else
|
|
{
|
|
frequency = 0U;
|
|
}
|
|
break;
|
|
}
|
|
case RCC_PERIPHCLK_ADC:
|
|
{
|
|
frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> RCC_CFGR_ADCPRE_Pos) + 1) * 2);
|
|
break;
|
|
}
|
|
default:
|
|
{
|
|
break;
|
|
}
|
|
}
|
|
return(frequency);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if defined(STM32F105xC) || defined(STM32F107xC)
|
|
/** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
|
|
* @brief PLLI2S Management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Extended PLLI2S Management functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control the PLLI2S
|
|
activation or deactivation
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable PLLI2S
|
|
* @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
|
|
* contains the configuration information for the PLLI2S
|
|
* @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
|
|
{
|
|
uint32_t tickstart = 0U;
|
|
|
|
/* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
|
|
if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
|
|
assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
|
|
|
|
/* Prediv2 can be written only when the PLL2 is disabled. */
|
|
/* Return an error only if new value is different from the programmed value */
|
|
if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
|
|
(__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Disable the main PLLI2S. */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLLI2S is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Configure the HSE prediv2 factor --------------------------------*/
|
|
__HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
|
|
|
|
|
|
/* Configure the main PLLI2S multiplication factors. */
|
|
__HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
|
|
|
|
/* Enable the main PLLI2S. */
|
|
__HAL_RCC_PLLI2S_ENABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLLI2S is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable PLLI2S
|
|
* @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
|
|
{
|
|
uint32_t tickstart = 0U;
|
|
|
|
/* Disable PLL I2S as not requested by I2S2 or I2S3*/
|
|
if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
|
|
{
|
|
/* Disable the main PLLI2S. */
|
|
__HAL_RCC_PLLI2S_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLLI2S is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
|
|
* @brief PLL2 Management functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Extended PLL2 Management functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control the PLL2
|
|
activation or deactivation
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable PLL2
|
|
* @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that
|
|
* contains the configuration information for the PLL2
|
|
* @note The PLL2 configuration not modified if used indirectly as system clock.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
|
|
{
|
|
uint32_t tickstart = 0U;
|
|
|
|
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
|
|
clock (i.e. it is used as PLL clock entry that is used as system clock). */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
|
|
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
|
|
((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
|
|
assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
|
|
|
|
/* Prediv2 can be written only when the PLLI2S is disabled. */
|
|
/* Return an error only if new value is different from the programmed value */
|
|
if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
|
|
(__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Disable the main PLL2. */
|
|
__HAL_RCC_PLL2_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL2 is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Configure the HSE prediv2 factor --------------------------------*/
|
|
__HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
|
|
|
|
/* Configure the main PLL2 multiplication factors. */
|
|
__HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
|
|
|
|
/* Enable the main PLL2. */
|
|
__HAL_RCC_PLL2_ENABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL2 is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Disable PLL2
|
|
* @note PLL2 is not disabled if used indirectly as system clock.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
|
|
{
|
|
uint32_t tickstart = 0U;
|
|
|
|
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
|
|
clock (i.e. it is used as PLL clock entry that is used as system clock). */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
|
|
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
|
|
((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL2. */
|
|
__HAL_RCC_PLL2_DISABLE();
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL2 is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* STM32F105xC || STM32F107xC */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
|