593 lines
25 KiB
C
593 lines
25 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_ll_system.h
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief Header file of SYSTEM LL module.
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The LL SYSTEM driver contains a set of generic APIs that can be
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used by user:
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(+) Some of the FLASH features need to be handled in the SYSTEM file.
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(+) Access to DBGCMU registers
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(+) Access to SYSCFG registers
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F1xx_LL_SYSTEM_H
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#define __STM32F1xx_LL_SYSTEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx.h"
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/** @addtogroup STM32F1xx_LL_Driver
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* @{
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*/
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#if defined (FLASH) || defined (DBGMCU)
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/** @defgroup SYSTEM_LL SYSTEM
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
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* @{
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*/
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
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* @{
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*/
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/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
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* @{
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*/
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#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
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#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
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#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
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#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
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#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
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* @{
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*/
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#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
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#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
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#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
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#if defined(DBGMCU_CR_DBG_TIM5_STOP)
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#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM5_STOP */
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#if defined(DBGMCU_CR_DBG_TIM6_STOP)
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#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM6_STOP */
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#if defined(DBGMCU_CR_DBG_TIM7_STOP)
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#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM7_STOP */
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#if defined(DBGMCU_CR_DBG_TIM12_STOP)
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#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM12_STOP */
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#if defined(DBGMCU_CR_DBG_TIM13_STOP)
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#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM13_STOP */
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#if defined(DBGMCU_CR_DBG_TIM14_STOP)
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#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM14_STOP */
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#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
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#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
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#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
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#if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT)
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#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
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#endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */
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#if defined(DBGMCU_CR_DBG_CAN1_STOP)
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#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
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#endif /* DBGMCU_CR_DBG_CAN1_STOP */
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#if defined(DBGMCU_CR_DBG_CAN2_STOP)
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#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
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#endif /* DBGMCU_CR_DBG_CAN2_STOP */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
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* @{
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*/
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#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
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#if defined(DBGMCU_CR_DBG_TIM8_STOP)
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#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_CAN1_STOP */
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#if defined(DBGMCU_CR_DBG_TIM9_STOP)
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#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM9_STOP */
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#if defined(DBGMCU_CR_DBG_TIM10_STOP)
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#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM10_STOP */
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#if defined(DBGMCU_CR_DBG_TIM11_STOP)
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#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM11_STOP */
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#if defined(DBGMCU_CR_DBG_TIM15_STOP)
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#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM15_STOP */
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#if defined(DBGMCU_CR_DBG_TIM16_STOP)
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#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM16_STOP */
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#if defined(DBGMCU_CR_DBG_TIM17_STOP)
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#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
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#endif /* DBGMCU_CR_DBG_TIM17_STOP */
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/**
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* @}
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*/
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/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
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* @{
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*/
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#if defined(FLASH_ACR_LATENCY)
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#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
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#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
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#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
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#else
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#endif /* FLASH_ACR_LATENCY */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
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* @{
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*/
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/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
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* @{
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*/
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/**
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* @brief Return the device identifier
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* @note For Low Density devices, the device ID is 0x412
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* @note For Medium Density devices, the device ID is 0x410
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* @note For High Density devices, the device ID is 0x414
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* @note For XL Density devices, the device ID is 0x430
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* @note For Connectivity Line devices, the device ID is 0x418
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* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
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* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
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*/
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__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
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{
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return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
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}
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/**
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* @brief Return the device revision identifier
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* @note This field indicates the revision of the device.
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For example, it is read as revA -> 0x1000,for Low Density devices
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For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices
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For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices
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For example, it is read as revA or 1 -> 0x1003,for XL Density devices
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For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices
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* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
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* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
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*/
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__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
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{
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return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
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}
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/**
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* @brief Enable the Debug Module during SLEEP mode
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* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
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{
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SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
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}
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/**
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* @brief Disable the Debug Module during SLEEP mode
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* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
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{
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CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
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}
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/**
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* @brief Enable the Debug Module during STOP mode
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* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
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{
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SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
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}
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/**
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* @brief Disable the Debug Module during STOP mode
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* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
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{
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CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
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}
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/**
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* @brief Enable the Debug Module during STANDBY mode
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* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
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{
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SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
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}
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/**
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* @brief Disable the Debug Module during STANDBY mode
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* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
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{
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CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
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}
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/**
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* @brief Set Trace pin assignment control
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* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
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* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
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* @param PinAssignment This parameter can be one of the following values:
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* @arg @ref LL_DBGMCU_TRACE_NONE
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* @arg @ref LL_DBGMCU_TRACE_ASYNCH
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* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
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* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
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* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
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{
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MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
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}
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/**
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* @brief Get Trace pin assignment control
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* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
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* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_DBGMCU_TRACE_NONE
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* @arg @ref LL_DBGMCU_TRACE_ASYNCH
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* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
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* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
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* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
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*/
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__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
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{
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return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
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}
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/**
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* @brief Freeze APB1 peripherals (group1 peripherals)
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* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
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* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
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* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
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{
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SET_BIT(DBGMCU->CR, Periphs);
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}
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/**
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* @brief Unfreeze APB1 peripherals (group1 peripherals)
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* @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
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* DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
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* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
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* @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
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* @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
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{
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CLEAR_BIT(DBGMCU->CR, Periphs);
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}
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/**
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* @brief Freeze APB2 peripherals
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* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
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{
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SET_BIT(DBGMCU->CR, Periphs);
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}
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/**
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* @brief Unfreeze APB2 peripherals
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* @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
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* DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*)
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* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*)
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*
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* (*) value not defined in all devices.
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* @retval None
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*/
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__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
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{
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CLEAR_BIT(DBGMCU->CR, Periphs);
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}
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/**
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* @}
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*/
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#if defined(FLASH_ACR_LATENCY)
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/** @defgroup SYSTEM_LL_EF_FLASH FLASH
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* @{
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*/
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/**
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* @brief Set FLASH Latency
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* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
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* @param Latency This parameter can be one of the following values:
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* @arg @ref LL_FLASH_LATENCY_0
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* @arg @ref LL_FLASH_LATENCY_1
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* @arg @ref LL_FLASH_LATENCY_2
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* @retval None
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*/
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__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
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{
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
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}
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/**
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* @brief Get FLASH Latency
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* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_FLASH_LATENCY_0
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* @arg @ref LL_FLASH_LATENCY_1
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* @arg @ref LL_FLASH_LATENCY_2
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*/
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__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
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{
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return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
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}
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/**
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* @brief Enable Prefetch
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* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
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* @retval None
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*/
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__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
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{
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SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
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}
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/**
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* @brief Disable Prefetch
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* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
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* @retval None
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*/
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__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
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{
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CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
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}
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/**
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* @brief Check if Prefetch buffer is enabled
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* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
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{
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return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
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}
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#endif /* FLASH_ACR_LATENCY */
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/**
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* @brief Enable Flash Half Cycle Access
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* @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
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* @retval None
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*/
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__STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
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{
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SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
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}
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/**
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* @brief Disable Flash Half Cycle Access
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* @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
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* @retval None
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*/
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__STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
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{
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CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
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}
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/**
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* @brief Check if Flash Half Cycle Access is enabled or not
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* @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
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{
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return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* defined (FLASH) || defined (DBGMCU) */
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F1xx_LL_SYSTEM_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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