303 lines
8.2 KiB
C
303 lines
8.2 KiB
C
// Hardware interface to "fullspeed USB controller" on stm32f1
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//
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// Copyright (C) 2018-2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <string.h> // NULL
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#include "autoconf.h" // CONFIG_STM32_FLASH_START_2000
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#include "board/armcm_boot.h" // armcm_enable_irq
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#include "board/armcm_timer.h" // udelay
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#include "board/gpio.h" // gpio_out_setup
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#include "board/io.h" // writeb
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#include "board/usb_cdc.h" // usb_notify_ep0
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#include "board/usb_cdc_ep.h" // USB_CDC_EP_BULK_IN
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // GPIO
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#include "sched.h" // DECL_INIT
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/****************************************************************
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* USB transfer memory
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****************************************************************/
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#if CONFIG_MACH_STM32F103
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typedef volatile uint32_t epmword_t;
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#else
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typedef volatile uint16_t epmword_t;
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#endif
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struct ep_desc {
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epmword_t addr_tx, count_tx, addr_rx, count_rx;
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};
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struct ep_mem {
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struct ep_desc ep0, ep_acm, ep_bulk_out, ep_bulk_in;
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epmword_t ep0_tx[USB_CDC_EP0_SIZE / 2];
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epmword_t ep0_rx[USB_CDC_EP0_SIZE / 2 + 1];
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epmword_t ep_acm_tx[USB_CDC_EP_ACM_SIZE / 2];
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epmword_t ep_bulk_out_rx[USB_CDC_EP_BULK_OUT_SIZE / 2 + 1];
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epmword_t ep_bulk_in_tx[USB_CDC_EP_BULK_IN_SIZE / 2];
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};
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#define EPM ((struct ep_mem *)USB_PMAADDR)
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#define CALC_ADDR(p) (((epmword_t*)(p) - (epmword_t*)EPM) * 2)
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#define CALC_SIZE(s) ((s) > 32 ? (DIV_ROUND_UP((s), 32) << 10) | 0x8000 \
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: DIV_ROUND_UP((s), 2) << 10)
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// Setup the transfer descriptors in dedicated usb memory
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static void
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btable_configure(void)
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{
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EPM->ep0.count_tx = 0;
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EPM->ep0.addr_tx = CALC_ADDR(EPM->ep0_tx);
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EPM->ep0.count_rx = CALC_SIZE(USB_CDC_EP0_SIZE);
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EPM->ep0.addr_rx = CALC_ADDR(EPM->ep0_rx);
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EPM->ep_acm.count_tx = 0;
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EPM->ep_acm.addr_tx = CALC_ADDR(EPM->ep_acm_tx);
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EPM->ep_bulk_out.count_rx = CALC_SIZE(USB_CDC_EP_BULK_OUT_SIZE);
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EPM->ep_bulk_out.addr_rx = CALC_ADDR(EPM->ep_bulk_out_rx);
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EPM->ep_bulk_in.count_tx = 0;
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EPM->ep_bulk_in.addr_tx = CALC_ADDR(EPM->ep_bulk_in_tx);
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}
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// Read a packet stored in dedicated usb memory
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static void
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btable_read_packet(uint8_t *dest, epmword_t *src, int count)
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{
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uint_fast8_t i;
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for (i=0; i<(count/2); i++) {
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uint32_t d = *src++;
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*dest++ = d;
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*dest++ = d >> 8;
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}
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if (count & 1)
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*dest = *src;
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}
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// Write a packet to dedicated usb memory
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static void
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btable_write_packet(epmword_t *dest, const uint8_t *src, int count)
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{
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int i;
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for (i=0; i<(count/2); i++) {
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uint8_t b1 = *src++, b2 = *src++;
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*dest++ = b1 | (b2 << 8);
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}
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if (count & 1)
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*dest = *src;
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}
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/****************************************************************
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* USB endpoint register
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****************************************************************/
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#define USB_EPR ((volatile uint32_t *)USB_BASE)
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#define EPR_RWBITS (USB_EPADDR_FIELD | USB_EP_KIND | USB_EP_TYPE_MASK)
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#define EPR_RWCBITS (USB_EP_CTR_RX | USB_EP_CTR_TX)
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static uint32_t
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set_stat_rx_bits(uint32_t epr, uint32_t bits)
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{
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return ((epr & (EPR_RWBITS | USB_EPRX_STAT)) ^ bits) | EPR_RWCBITS;
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}
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static uint32_t
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set_stat_tx_bits(uint32_t epr, uint32_t bits)
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{
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return ((epr & (EPR_RWBITS | USB_EPTX_STAT)) ^ bits) | EPR_RWCBITS;
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}
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static uint32_t
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set_stat_rxtx_bits(uint32_t epr, uint32_t bits)
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{
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uint32_t mask = EPR_RWBITS | USB_EPRX_STAT | USB_EPTX_STAT;
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return ((epr & mask) ^ bits) | EPR_RWCBITS;
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}
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/****************************************************************
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* USB interface
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****************************************************************/
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int_fast8_t
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usb_read_bulk_out(void *data, uint_fast8_t max_len)
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{
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uint32_t epr = USB_EPR[USB_CDC_EP_BULK_OUT];
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if ((epr & USB_EPRX_STAT) == USB_EP_RX_VALID)
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// No data ready
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return -1;
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uint32_t count = EPM->ep_bulk_out.count_rx & 0x3ff;
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if (count > max_len)
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count = max_len;
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btable_read_packet(data, EPM->ep_bulk_out_rx, count);
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USB_EPR[USB_CDC_EP_BULK_OUT] = set_stat_rx_bits(epr, USB_EP_RX_VALID);
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return count;
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}
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int_fast8_t
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usb_send_bulk_in(void *data, uint_fast8_t len)
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{
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uint32_t epr = USB_EPR[USB_CDC_EP_BULK_IN];
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if ((epr & USB_EPTX_STAT) != USB_EP_TX_NAK)
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// No buffer space available
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return -1;
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btable_write_packet(EPM->ep_bulk_in_tx, data, len);
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EPM->ep_bulk_in.count_tx = len;
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USB_EPR[USB_CDC_EP_BULK_IN] = set_stat_tx_bits(epr, USB_EP_TX_VALID);
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return len;
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}
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int_fast8_t
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usb_read_ep0(void *data, uint_fast8_t max_len)
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{
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uint32_t epr = USB_EPR[0];
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if ((epr & USB_EPRX_STAT) != USB_EP_RX_NAK)
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// No data ready
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return -1;
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uint32_t count = EPM->ep0.count_rx & 0x3ff;
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if (count > max_len)
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count = max_len;
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btable_read_packet(data, EPM->ep0_rx, count);
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USB_EPR[0] = set_stat_rxtx_bits(epr, USB_EP_RX_VALID | USB_EP_TX_NAK);
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return count;
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}
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int_fast8_t
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usb_read_ep0_setup(void *data, uint_fast8_t max_len)
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{
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return usb_read_ep0(data, max_len);
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}
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int_fast8_t
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usb_send_ep0(const void *data, uint_fast8_t len)
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{
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uint32_t epr = USB_EPR[0];
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if ((epr & USB_EPRX_STAT) != USB_EP_RX_VALID)
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// Transfer interrupted
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return -2;
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if ((epr & USB_EPTX_STAT) != USB_EP_TX_NAK)
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// No buffer space available
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return -1;
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btable_write_packet(EPM->ep0_tx, data, len);
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EPM->ep0.count_tx = len;
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USB_EPR[0] = set_stat_tx_bits(epr, USB_EP_TX_VALID);
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return len;
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}
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void
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usb_stall_ep0(void)
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{
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USB_EPR[0] = set_stat_rxtx_bits(USB_EPR[0]
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, USB_EP_RX_STALL | USB_EP_TX_STALL);
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}
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static uint8_t set_address;
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void
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usb_set_address(uint_fast8_t addr)
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{
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writeb(&set_address, addr | USB_DADDR_EF);
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usb_send_ep0(NULL, 0);
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}
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void
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usb_set_configure(void)
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{
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}
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/****************************************************************
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* Setup and interrupts
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****************************************************************/
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// Configure interface after a USB reset event
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static void
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usb_reset(void)
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{
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USB_EPR[0] = 0 | USB_EP_CONTROL | USB_EP_RX_VALID | USB_EP_TX_NAK;
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USB_EPR[USB_CDC_EP_ACM] = (USB_CDC_EP_ACM | USB_EP_INTERRUPT
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| USB_EP_RX_NAK | USB_EP_TX_NAK);
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USB_EPR[USB_CDC_EP_BULK_OUT] = (USB_CDC_EP_BULK_OUT | USB_EP_BULK
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| USB_EP_RX_VALID | USB_EP_TX_NAK);
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USB_EPR[USB_CDC_EP_BULK_IN] = (USB_CDC_EP_BULK_IN | USB_EP_BULK
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| USB_EP_RX_NAK | USB_EP_TX_NAK);
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USB->CNTR = USB_CNTR_CTRM | USB_CNTR_RESETM;
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USB->DADDR = USB_DADDR_EF;
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}
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// Main irq handler
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void
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USB_IRQHandler(void)
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{
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uint32_t istr = USB->ISTR;
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if (istr & USB_ISTR_CTR) {
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// Endpoint activity
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uint32_t ep = istr & USB_ISTR_EP_ID;
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uint32_t epr = USB_EPR[ep];
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USB_EPR[ep] = epr & EPR_RWBITS;
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if (ep == 0) {
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usb_notify_ep0();
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if (epr & USB_EP_CTR_TX && set_address) {
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// Apply address after last "in" message transmitted
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USB->DADDR = set_address;
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set_address = 0;
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}
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} else if (ep == USB_CDC_EP_BULK_OUT) {
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usb_notify_bulk_out();
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} else if (ep == USB_CDC_EP_BULK_IN) {
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usb_notify_bulk_in();
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}
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}
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if (istr & USB_ISTR_RESET) {
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// USB Reset
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USB->ISTR = (uint16_t)~USB_ISTR_RESET;
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usb_reset();
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}
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}
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DECL_CONSTANT_STR("RESERVE_PINS_USB", "PA11,PA12");
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// Initialize the usb controller
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void
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usb_init(void)
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{
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if (CONFIG_MACH_STM32F1) {
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// Pull the D+ pin low briefly to signal a new connection
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gpio_out_setup(GPIO('A', 12), 0);
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udelay(5000);
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gpio_in_setup(GPIO('A', 12), 0);
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}
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// Enable USB clock
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enable_pclock(USB_BASE);
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// Setup USB packet memory
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btable_configure();
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// Enable USB pullup
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#ifdef USB_BCDR_DPPU
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USB->BCDR = USB_BCDR_DPPU;
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#endif
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// Reset usb controller and enable interrupts
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USB->CNTR = USB_CNTR_FRES;
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USB->BTABLE = 0;
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USB->DADDR = 0;
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USB->CNTR = USB_CNTR_RESETM;
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USB->ISTR = 0;
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#if CONFIG_MACH_STM32F103
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armcm_enable_irq(USB_IRQHandler, USB_LP_IRQn, 1);
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#elif CONFIG_MACH_STM32F0
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armcm_enable_irq(USB_IRQHandler, USB_IRQn, 1);
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#endif
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}
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DECL_INIT(usb_init);
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