580 lines
29 KiB
C
580 lines
29 KiB
C
/**
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******************************************************************************
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* @file stm32f0xx_hal_dma.h
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* @author MCD Application Team
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* @brief Header file of DMA HAL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F0xx_HAL_DMA_H
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#define __STM32F0xx_HAL_DMA_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx_hal_def.h"
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/** @addtogroup STM32F0xx_HAL_Driver
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* @{
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*/
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/** @addtogroup DMA
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup DMA_Exported_Types DMA Exported Types
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* @{
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*/
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/**
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* @brief DMA Configuration Structure definition
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*/
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typedef struct
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{
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uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
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from memory to memory or from peripheral to memory.
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This parameter can be a value of @ref DMA_Data_transfer_direction */
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uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
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This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
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uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
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This parameter can be a value of @ref DMA_Memory_incremented_mode */
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uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
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This parameter can be a value of @ref DMA_Peripheral_data_size */
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uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
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This parameter can be a value of @ref DMA_Memory_data_size */
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uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
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This parameter can be a value of @ref DMA_mode
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@note The circular buffer mode cannot be used if the memory-to-memory
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data transfer is configured on the selected Channel */
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uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
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This parameter can be a value of @ref DMA_Priority_level */
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} DMA_InitTypeDef;
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/**
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* @brief HAL DMA State structures definition
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*/
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typedef enum
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{
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HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
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HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
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HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
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HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
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}HAL_DMA_StateTypeDef;
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/**
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* @brief HAL DMA Error Code structure definition
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*/
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typedef enum
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{
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HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
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HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
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}HAL_DMA_LevelCompleteTypeDef;
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/**
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* @brief HAL DMA Callback ID structure definition
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*/
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typedef enum
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{
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HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
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HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
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HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
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HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
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HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
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}HAL_DMA_CallbackIDTypeDef;
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/**
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* @brief DMA handle Structure definition
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*/
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typedef struct __DMA_HandleTypeDef
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{
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DMA_Channel_TypeDef *Instance; /*!< Register base address */
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DMA_InitTypeDef Init; /*!< DMA communication parameters */
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HAL_LockTypeDef Lock; /*!< DMA locking object */
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__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
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void *Parent; /*!< Parent object state */
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void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
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void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
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void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
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void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
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__IO uint32_t ErrorCode; /*!< DMA Error code */
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DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
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uint32_t ChannelIndex; /*!< DMA Channel Index */
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} DMA_HandleTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup DMA_Exported_Constants DMA Exported Constants
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* @{
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*/
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/** @defgroup DMA_Error_Code DMA Error Code
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* @{
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*/
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#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
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#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
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#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
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#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
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#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
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/**
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* @}
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*/
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/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
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* @{
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*/
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#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
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#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
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#define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
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* @{
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*/
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#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
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#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
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/**
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* @}
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*/
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/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
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* @{
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*/
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#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
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#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
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/**
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* @}
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*/
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/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
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* @{
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*/
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#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
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#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
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#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
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/**
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* @}
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*/
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/** @defgroup DMA_Memory_data_size DMA Memory data size
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* @{
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*/
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#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
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#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
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#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
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/**
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* @}
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*/
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/** @defgroup DMA_mode DMA mode
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* @{
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*/
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#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
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#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
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/**
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* @}
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*/
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/** @defgroup DMA_Priority_level DMA Priority level
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* @{
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*/
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#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
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#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
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#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
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#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
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/**
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* @}
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*/
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/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
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* @{
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*/
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#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
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#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
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#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
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/**
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* @}
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*/
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/** @defgroup DMA_flag_definitions DMA flag definitions
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* @{
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*/
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#define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */
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#define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */
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#define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */
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#define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */
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#define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */
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#define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */
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#define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */
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#define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */
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#define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */
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#define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */
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#define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */
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#define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */
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#define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */
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#define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */
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#define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */
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#define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */
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#define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */
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#define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */
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#define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */
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#define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */
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#define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */
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#define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */
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#define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */
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#define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */
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#define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */
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#define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */
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#define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */
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#define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */
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/**
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* @}
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*/
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#if defined(SYSCFG_CFGR1_DMA_RMP)
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/** @defgroup HAL_DMA_remapping HAL DMA remapping
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* Elements values convention: 0xYYYYYYYY
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* - YYYYYYYY : Position in the SYSCFG register CFGR1
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* @{
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*/
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#define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
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0: No remap (ADC DMA requests mapped on DMA channel 1
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1: Remap (ADC DMA requests mapped on DMA channel 2 */
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#define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
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0: No remap (USART1_TX DMA request mapped on DMA channel 2
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1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
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#define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
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0: No remap (USART1_RX DMA request mapped on DMA channel 3
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1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
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#define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
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0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
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1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
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#define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
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0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
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1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
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#if defined (STM32F070xB)
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#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
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0: Disabled, need to remap before use
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1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
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#endif
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#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
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#define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
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0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
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1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
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#define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
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0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
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1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
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#define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
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0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
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1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
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#define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
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0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
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1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
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#define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
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0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
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1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
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#define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
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0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
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1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
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#define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
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0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
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1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
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#define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
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0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
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1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
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#define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
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0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
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1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
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#endif
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/**
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* @}
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*/
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#endif /* SYSCFG_CFGR1_DMA_RMP */
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup DMA_Exported_Macros DMA Exported Macros
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* @{
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*/
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/** @brief Reset DMA handle state
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* @param __HANDLE__ DMA handle.
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* @retval None
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*/
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#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
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/**
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* @brief Enable the specified DMA Channel.
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* @param __HANDLE__ DMA handle
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* @retval None
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*/
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#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
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/**
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* @brief Disable the specified DMA Channel.
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* @param __HANDLE__ DMA handle
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* @retval None
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*/
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#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
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/* Interrupt & Flag management */
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/**
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* @brief Enables the specified DMA Channel interrupts.
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* @param __HANDLE__ DMA handle
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* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
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* This parameter can be any combination of the following values:
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* @arg DMA_IT_TC: Transfer complete interrupt mask
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* @arg DMA_IT_HT: Half transfer complete interrupt mask
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* @arg DMA_IT_TE: Transfer error interrupt mask
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* @retval None
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*/
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#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
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/**
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* @brief Disables the specified DMA Channel interrupts.
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* @param __HANDLE__ DMA handle
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* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
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* This parameter can be any combination of the following values:
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* @arg DMA_IT_TC: Transfer complete interrupt mask
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* @arg DMA_IT_HT: Half transfer complete interrupt mask
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* @arg DMA_IT_TE: Transfer error interrupt mask
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* @retval None
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*/
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#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
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/**
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* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
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* @param __HANDLE__ DMA handle
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* @param __INTERRUPT__ specifies the DMA interrupt source to check.
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* This parameter can be one of the following values:
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* @arg DMA_IT_TC: Transfer complete interrupt mask
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* @arg DMA_IT_HT: Half transfer complete interrupt mask
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* @arg DMA_IT_TE: Transfer error interrupt mask
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* @retval The state of DMA_IT (SET or RESET).
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*/
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#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
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/**
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* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
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* @param __HANDLE__ DMA handle
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*
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* @retval The number of remaining data units in the current DMA Channel transfer.
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*/
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#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
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#if defined(SYSCFG_CFGR1_DMA_RMP)
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/** @brief DMA remapping enable/disable macros
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* @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping
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*/
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#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
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SYSCFG->CFGR1 |= (__DMA_REMAP__); \
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}while(0)
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#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
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SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
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}while(0)
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#endif /* SYSCFG_CFGR1_DMA_RMP */
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/**
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* @}
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*/
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/* Include DMA HAL Extension module */
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#include "stm32f0xx_hal_dma_ex.h"
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup DMA_Exported_Functions
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* @{
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*/
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/** @addtogroup DMA_Exported_Functions_Group1
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* @{
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*/
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/* Initialization and de-initialization functions *****************************/
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HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
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HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
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/**
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* @}
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*/
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/** @addtogroup DMA_Exported_Functions_Group2
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* @{
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*/
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/* Input and Output operation functions *****************************************************/
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HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
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HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
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HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
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HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
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void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
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HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
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HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
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/**
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* @}
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*/
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/** @addtogroup DMA_Exported_Functions_Group3
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* @{
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*/
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/* Peripheral State and Error functions ***************************************/
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HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
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uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
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/**
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* @}
|
|
*/
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|
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/**
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* @}
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*/
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|
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/** @addtogroup DMA_Private_Macros
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|
* @{
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|
*/
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|
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
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((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
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((DIRECTION) == DMA_MEMORY_TO_MEMORY))
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|
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
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|
((STATE) == DMA_PINC_DISABLE))
|
|
|
|
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
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|
((STATE) == DMA_MINC_DISABLE))
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|
|
|
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
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|
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
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|
((SIZE) == DMA_PDATAALIGN_WORD))
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|
|
|
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
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|
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
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|
((SIZE) == DMA_MDATAALIGN_WORD ))
|
|
|
|
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
|
|
((MODE) == DMA_CIRCULAR))
|
|
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
|
|
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
|
|
((PRIORITY) == DMA_PRIORITY_HIGH) || \
|
|
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
|
|
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
|
|
|
|
#if defined(SYSCFG_CFGR1_DMA_RMP)
|
|
|
|
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
|
|
#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
|
|
((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
|
|
((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
|
|
((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
|
|
((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
|
|
((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
|
|
((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
|
|
((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
|
|
((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
|
|
((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
|
|
((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
|
|
((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
|
|
((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
|
|
((RMP) == DMA_REMAP_TIM3_DMA_CH6))
|
|
#elif defined (STM32F070xB)
|
|
#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
|
|
((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
|
|
((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
|
|
((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
|
|
((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
|
|
((RMP) == DMA_REMAP_TIM17_DMA_CH2))
|
|
#else
|
|
#define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
|
|
((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
|
|
((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
|
|
((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
|
|
((RMP) == DMA_REMAP_TIM17_DMA_CH2))
|
|
#endif
|
|
|
|
#endif /* SYSCFG_CFGR1_DMA_RMP */
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32F0xx_HAL_DMA_H */
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
|
|