82 lines
4.5 KiB
C
82 lines
4.5 KiB
C
/**
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* \file
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*
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* \brief Instance description for TWIHS1
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_TWIHS1_INSTANCE_H_
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#define _SAME70_TWIHS1_INSTANCE_H_
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/* ========== Register definition for TWIHS1 peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TWIHS1_CR (0x4001C000) /**< (TWIHS1) Control Register */
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#define REG_TWIHS1_MMR (0x4001C004) /**< (TWIHS1) Master Mode Register */
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#define REG_TWIHS1_SMR (0x4001C008) /**< (TWIHS1) Slave Mode Register */
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#define REG_TWIHS1_IADR (0x4001C00C) /**< (TWIHS1) Internal Address Register */
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#define REG_TWIHS1_CWGR (0x4001C010) /**< (TWIHS1) Clock Waveform Generator Register */
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#define REG_TWIHS1_SR (0x4001C020) /**< (TWIHS1) Status Register */
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#define REG_TWIHS1_IER (0x4001C024) /**< (TWIHS1) Interrupt Enable Register */
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#define REG_TWIHS1_IDR (0x4001C028) /**< (TWIHS1) Interrupt Disable Register */
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#define REG_TWIHS1_IMR (0x4001C02C) /**< (TWIHS1) Interrupt Mask Register */
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#define REG_TWIHS1_RHR (0x4001C030) /**< (TWIHS1) Receive Holding Register */
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#define REG_TWIHS1_THR (0x4001C034) /**< (TWIHS1) Transmit Holding Register */
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#define REG_TWIHS1_SMBTR (0x4001C038) /**< (TWIHS1) SMBus Timing Register */
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#define REG_TWIHS1_FILTR (0x4001C044) /**< (TWIHS1) Filter Register */
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#define REG_TWIHS1_SWMR (0x4001C04C) /**< (TWIHS1) SleepWalking Matching Register */
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#define REG_TWIHS1_WPMR (0x4001C0E4) /**< (TWIHS1) Write Protection Mode Register */
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#define REG_TWIHS1_WPSR (0x4001C0E8) /**< (TWIHS1) Write Protection Status Register */
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#else
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#define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< (TWIHS1) Control Register */
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#define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< (TWIHS1) Master Mode Register */
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#define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< (TWIHS1) Slave Mode Register */
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#define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< (TWIHS1) Internal Address Register */
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#define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< (TWIHS1) Clock Waveform Generator Register */
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#define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< (TWIHS1) Status Register */
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#define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< (TWIHS1) Interrupt Enable Register */
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#define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< (TWIHS1) Interrupt Disable Register */
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#define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< (TWIHS1) Interrupt Mask Register */
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#define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< (TWIHS1) Receive Holding Register */
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#define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< (TWIHS1) Transmit Holding Register */
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#define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< (TWIHS1) SMBus Timing Register */
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#define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< (TWIHS1) Filter Register */
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#define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< (TWIHS1) SleepWalking Matching Register */
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#define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< (TWIHS1) Write Protection Mode Register */
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#define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< (TWIHS1) Write Protection Status Register */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for TWIHS1 peripheral ========== */
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#define TWIHS1_DMAC_ID_RX 17
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#define TWIHS1_DMAC_ID_TX 16
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#define TWIHS1_INSTANCE_ID 20
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#define TWIHS1_CLOCK_ID 20
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#endif /* _SAME70_TWIHS1_INSTANCE_ */
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