82 lines
4.4 KiB
C
82 lines
4.4 KiB
C
/**
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* \file
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*
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* \brief Instance description for QSPI
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_QSPI_INSTANCE_H_
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#define _SAME70_QSPI_INSTANCE_H_
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/* ========== Register definition for QSPI peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_QSPI_CR (0x4007C000) /**< (QSPI) Control Register */
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#define REG_QSPI_MR (0x4007C004) /**< (QSPI) Mode Register */
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#define REG_QSPI_RDR (0x4007C008) /**< (QSPI) Receive Data Register */
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#define REG_QSPI_TDR (0x4007C00C) /**< (QSPI) Transmit Data Register */
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#define REG_QSPI_SR (0x4007C010) /**< (QSPI) Status Register */
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#define REG_QSPI_IER (0x4007C014) /**< (QSPI) Interrupt Enable Register */
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#define REG_QSPI_IDR (0x4007C018) /**< (QSPI) Interrupt Disable Register */
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#define REG_QSPI_IMR (0x4007C01C) /**< (QSPI) Interrupt Mask Register */
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#define REG_QSPI_SCR (0x4007C020) /**< (QSPI) Serial Clock Register */
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#define REG_QSPI_IAR (0x4007C030) /**< (QSPI) Instruction Address Register */
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#define REG_QSPI_ICR (0x4007C034) /**< (QSPI) Instruction Code Register */
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#define REG_QSPI_IFR (0x4007C038) /**< (QSPI) Instruction Frame Register */
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#define REG_QSPI_SMR (0x4007C040) /**< (QSPI) Scrambling Mode Register */
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#define REG_QSPI_SKR (0x4007C044) /**< (QSPI) Scrambling Key Register */
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#define REG_QSPI_WPMR (0x4007C0E4) /**< (QSPI) Write Protection Mode Register */
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#define REG_QSPI_WPSR (0x4007C0E8) /**< (QSPI) Write Protection Status Register */
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#else
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#define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< (QSPI) Control Register */
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#define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< (QSPI) Mode Register */
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#define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< (QSPI) Receive Data Register */
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#define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< (QSPI) Transmit Data Register */
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#define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< (QSPI) Status Register */
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#define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< (QSPI) Interrupt Enable Register */
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#define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< (QSPI) Interrupt Disable Register */
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#define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< (QSPI) Interrupt Mask Register */
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#define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< (QSPI) Serial Clock Register */
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#define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< (QSPI) Instruction Address Register */
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#define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< (QSPI) Instruction Code Register */
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#define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< (QSPI) Instruction Frame Register */
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#define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< (QSPI) Scrambling Mode Register */
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#define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< (QSPI) Scrambling Key Register */
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#define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< (QSPI) Write Protection Mode Register */
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#define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< (QSPI) Write Protection Status Register */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for QSPI peripheral ========== */
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#define QSPI_DMAC_ID_RX 6
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#define QSPI_DMAC_ID_TX 5
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#define QSPI_INSTANCE_ID 43
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#define QSPI_CLOCK_ID 43
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#endif /* _SAME70_QSPI_INSTANCE_ */
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