77 lines
6.4 KiB
C
77 lines
6.4 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4S_UART0_INSTANCE_
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#define _SAM4S_UART0_INSTANCE_
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/* ========== Register definition for UART0 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_UART0_CR (0x400E0600U) /**< \brief (UART0) Control Register */
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#define REG_UART0_MR (0x400E0604U) /**< \brief (UART0) Mode Register */
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#define REG_UART0_IER (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
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#define REG_UART0_IDR (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
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#define REG_UART0_IMR (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
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#define REG_UART0_SR (0x400E0614U) /**< \brief (UART0) Status Register */
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#define REG_UART0_RHR (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
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#define REG_UART0_THR (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
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#define REG_UART0_BRGR (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
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#define REG_UART0_RPR (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
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#define REG_UART0_RCR (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
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#define REG_UART0_TPR (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
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#define REG_UART0_TCR (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
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#define REG_UART0_RNPR (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
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#define REG_UART0_RNCR (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
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#define REG_UART0_TNPR (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
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#define REG_UART0_TNCR (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
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#define REG_UART0_PTCR (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
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#define REG_UART0_PTSR (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
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#else
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#define REG_UART0_CR (*(__O uint32_t*)0x400E0600U) /**< \brief (UART0) Control Register */
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#define REG_UART0_MR (*(__IO uint32_t*)0x400E0604U) /**< \brief (UART0) Mode Register */
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#define REG_UART0_IER (*(__O uint32_t*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
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#define REG_UART0_IDR (*(__O uint32_t*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
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#define REG_UART0_IMR (*(__I uint32_t*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
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#define REG_UART0_SR (*(__I uint32_t*)0x400E0614U) /**< \brief (UART0) Status Register */
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#define REG_UART0_RHR (*(__I uint32_t*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
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#define REG_UART0_THR (*(__O uint32_t*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
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#define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
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#define REG_UART0_RPR (*(__IO uint32_t*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
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#define REG_UART0_RCR (*(__IO uint32_t*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
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#define REG_UART0_TPR (*(__IO uint32_t*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
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#define REG_UART0_TCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
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#define REG_UART0_RNPR (*(__IO uint32_t*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
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#define REG_UART0_RNCR (*(__IO uint32_t*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
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#define REG_UART0_TNPR (*(__IO uint32_t*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
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#define REG_UART0_TNCR (*(__IO uint32_t*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
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#define REG_UART0_PTCR (*(__O uint32_t*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
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#define REG_UART0_PTSR (*(__I uint32_t*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4S_UART0_INSTANCE_ */
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