188 lines
8.9 KiB
C
188 lines
8.9 KiB
C
/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : XIP
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// Version : 1
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// Bus type : ahb
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// Description : QSPI flash execute-in-place block
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// =============================================================================
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#ifndef HARDWARE_REGS_XIP_DEFINED
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#define HARDWARE_REGS_XIP_DEFINED
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// =============================================================================
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// Register : XIP_CTRL
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// Description : Cache control
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#define XIP_CTRL_OFFSET _u(0x00000000)
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#define XIP_CTRL_BITS _u(0x0000000b)
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#define XIP_CTRL_RESET _u(0x00000003)
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// -----------------------------------------------------------------------------
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// Field : XIP_CTRL_POWER_DOWN
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// Description : When 1, the cache memories are powered down. They retain state,
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// but can not be accessed. This reduces static power dissipation.
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// Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache
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// cannot
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// be enabled when powered down.
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// Cache-as-SRAM accesses will produce a bus error response when
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// the cache is powered down.
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#define XIP_CTRL_POWER_DOWN_RESET _u(0x0)
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#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008)
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#define XIP_CTRL_POWER_DOWN_MSB _u(3)
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#define XIP_CTRL_POWER_DOWN_LSB _u(3)
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#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : XIP_CTRL_ERR_BADWRITE
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// Description : When 1, writes to any alias other than 0x0 (caching,
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// allocating)
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// will produce a bus fault. When 0, these writes are silently
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// ignored.
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// In either case, writes to the 0x0 alias will deallocate on tag
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// match,
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// as usual.
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#define XIP_CTRL_ERR_BADWRITE_RESET _u(0x1)
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#define XIP_CTRL_ERR_BADWRITE_BITS _u(0x00000002)
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#define XIP_CTRL_ERR_BADWRITE_MSB _u(1)
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#define XIP_CTRL_ERR_BADWRITE_LSB _u(1)
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#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : XIP_CTRL_EN
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// Description : When 1, enable the cache. When the cache is disabled, all XIP
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// accesses
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// will go straight to the flash, without querying the cache. When
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// enabled,
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// cacheable XIP accesses will query the cache, and the flash will
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// not be accessed if the tag matches and the valid bit is set.
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//
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// If the cache is enabled, cache-as-SRAM accesses have no effect
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// on the
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// cache data RAM, and will produce a bus error response.
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#define XIP_CTRL_EN_RESET _u(0x1)
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#define XIP_CTRL_EN_BITS _u(0x00000001)
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#define XIP_CTRL_EN_MSB _u(0)
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#define XIP_CTRL_EN_LSB _u(0)
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#define XIP_CTRL_EN_ACCESS "RW"
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// =============================================================================
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// Register : XIP_FLUSH
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// Description : Cache Flush control
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// Write 1 to flush the cache. This clears the tag memory, but
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// the data memory retains its contents. (This means cache-as-SRAM
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// contents is not affected by flush or reset.)
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// Reading will hold the bus (stall the processor) until the flush
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// completes. Alternatively STAT can be polled until completion.
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#define XIP_FLUSH_OFFSET _u(0x00000004)
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#define XIP_FLUSH_BITS _u(0x00000001)
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#define XIP_FLUSH_RESET _u(0x00000000)
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#define XIP_FLUSH_MSB _u(0)
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#define XIP_FLUSH_LSB _u(0)
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#define XIP_FLUSH_ACCESS "SC"
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// =============================================================================
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// Register : XIP_STAT
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// Description : Cache Status
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#define XIP_STAT_OFFSET _u(0x00000008)
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#define XIP_STAT_BITS _u(0x00000007)
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#define XIP_STAT_RESET _u(0x00000002)
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// -----------------------------------------------------------------------------
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// Field : XIP_STAT_FIFO_FULL
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// Description : When 1, indicates the XIP streaming FIFO is completely full.
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// The streaming FIFO is 2 entries deep, so the full and empty
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// flag allow its level to be ascertained.
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#define XIP_STAT_FIFO_FULL_RESET _u(0x0)
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#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004)
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#define XIP_STAT_FIFO_FULL_MSB _u(2)
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#define XIP_STAT_FIFO_FULL_LSB _u(2)
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#define XIP_STAT_FIFO_FULL_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : XIP_STAT_FIFO_EMPTY
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// Description : When 1, indicates the XIP streaming FIFO is completely empty.
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#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1)
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#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002)
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#define XIP_STAT_FIFO_EMPTY_MSB _u(1)
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#define XIP_STAT_FIFO_EMPTY_LSB _u(1)
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#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : XIP_STAT_FLUSH_READY
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// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise.
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// The cache is flushed whenever the XIP block is reset, and also
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// when requested via the FLUSH register.
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#define XIP_STAT_FLUSH_READY_RESET _u(0x0)
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#define XIP_STAT_FLUSH_READY_BITS _u(0x00000001)
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#define XIP_STAT_FLUSH_READY_MSB _u(0)
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#define XIP_STAT_FLUSH_READY_LSB _u(0)
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#define XIP_STAT_FLUSH_READY_ACCESS "RO"
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// =============================================================================
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// Register : XIP_CTR_HIT
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// Description : Cache Hit counter
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// A 32 bit saturating counter that increments upon each cache
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// hit,
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// i.e. when an XIP access is serviced directly from cached data.
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// Write any value to clear.
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#define XIP_CTR_HIT_OFFSET _u(0x0000000c)
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#define XIP_CTR_HIT_BITS _u(0xffffffff)
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#define XIP_CTR_HIT_RESET _u(0x00000000)
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#define XIP_CTR_HIT_MSB _u(31)
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#define XIP_CTR_HIT_LSB _u(0)
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#define XIP_CTR_HIT_ACCESS "WC"
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// =============================================================================
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// Register : XIP_CTR_ACC
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// Description : Cache Access counter
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// A 32 bit saturating counter that increments upon each XIP
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// access,
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// whether the cache is hit or not. This includes noncacheable
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// accesses.
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// Write any value to clear.
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#define XIP_CTR_ACC_OFFSET _u(0x00000010)
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#define XIP_CTR_ACC_BITS _u(0xffffffff)
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#define XIP_CTR_ACC_RESET _u(0x00000000)
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#define XIP_CTR_ACC_MSB _u(31)
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#define XIP_CTR_ACC_LSB _u(0)
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#define XIP_CTR_ACC_ACCESS "WC"
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// =============================================================================
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// Register : XIP_STREAM_ADDR
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// Description : FIFO stream address
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// The address of the next word to be streamed from flash to the
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// streaming FIFO.
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// Increments automatically after each flash access.
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// Write the initial access address here before starting a
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// streaming read.
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#define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
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#define XIP_STREAM_ADDR_BITS _u(0xfffffffc)
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#define XIP_STREAM_ADDR_RESET _u(0x00000000)
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#define XIP_STREAM_ADDR_MSB _u(31)
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#define XIP_STREAM_ADDR_LSB _u(2)
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#define XIP_STREAM_ADDR_ACCESS "RW"
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// =============================================================================
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// Register : XIP_STREAM_CTR
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// Description : FIFO stream control
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// Write a nonzero value to start a streaming read. This will then
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// progress in the background, using flash idle cycles to transfer
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// a linear data block from flash to the streaming FIFO.
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// Decrements automatically (1 at a time) as the stream
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// progresses, and halts on reaching 0.
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// Write 0 to halt an in-progress stream, and discard any
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// in-flight
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// read, so that a new stream can immediately be started (after
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// draining the FIFO and reinitialising STREAM_ADDR)
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#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
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#define XIP_STREAM_CTR_BITS _u(0x003fffff)
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#define XIP_STREAM_CTR_RESET _u(0x00000000)
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#define XIP_STREAM_CTR_MSB _u(21)
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#define XIP_STREAM_CTR_LSB _u(0)
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#define XIP_STREAM_CTR_ACCESS "RW"
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// =============================================================================
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// Register : XIP_STREAM_FIFO
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// Description : FIFO stream data
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// Streamed data is buffered here, for retrieval by the system
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// DMA.
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// This FIFO can also be accessed via the XIP_AUX slave, to avoid
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// exposing
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// the DMA to bus stalls caused by other XIP traffic.
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#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
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#define XIP_STREAM_FIFO_BITS _u(0xffffffff)
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#define XIP_STREAM_FIFO_RESET _u(0x00000000)
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#define XIP_STREAM_FIFO_MSB _u(31)
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#define XIP_STREAM_FIFO_LSB _u(0)
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#define XIP_STREAM_FIFO_ACCESS "RF"
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// =============================================================================
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#endif // HARDWARE_REGS_XIP_DEFINED
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