152 lines
7.7 KiB
C
152 lines
7.7 KiB
C
/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : VREG_AND_CHIP_RESET
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// Version : 1
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// Bus type : apb
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// Description : control and status for on-chip voltage regulator and chip
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// level reset subsystem
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// =============================================================================
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#ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
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#define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
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// =============================================================================
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// Register : VREG_AND_CHIP_RESET_VREG
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// Description : Voltage regulator control and status
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#define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000)
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#define VREG_AND_CHIP_RESET_VREG_BITS _u(0x000010f3)
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#define VREG_AND_CHIP_RESET_VREG_RESET _u(0x000000b1)
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_VREG_ROK
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// Description : regulation status
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// 0=not in regulation, 1=in regulation
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#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _u(0x0)
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#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _u(0x00001000)
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#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _u(12)
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#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _u(12)
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#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_VREG_VSEL
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// Description : output voltage select
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// 0000 to 0101 - 0.80V
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// 0110 - 0.85V
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// 0111 - 0.90V
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// 1000 - 0.95V
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// 1001 - 1.00V
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// 1010 - 1.05V
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// 1011 - 1.10V (default)
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// 1100 - 1.15V
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// 1101 - 1.20V
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// 1110 - 1.25V
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// 1111 - 1.30V
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#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _u(0xb)
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#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _u(0x000000f0)
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#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _u(7)
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#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _u(4)
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#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_VREG_HIZ
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// Description : high impedance mode select
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// 0=not in high impedance mode, 1=in high impedance mode
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#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _u(0x0)
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#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _u(0x00000002)
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#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _u(1)
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#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _u(1)
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#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_VREG_EN
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// Description : enable
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// 0=not enabled, 1=enabled
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#define VREG_AND_CHIP_RESET_VREG_EN_RESET _u(0x1)
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#define VREG_AND_CHIP_RESET_VREG_EN_BITS _u(0x00000001)
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#define VREG_AND_CHIP_RESET_VREG_EN_MSB _u(0)
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#define VREG_AND_CHIP_RESET_VREG_EN_LSB _u(0)
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#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW"
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// =============================================================================
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// Register : VREG_AND_CHIP_RESET_BOD
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// Description : brown-out detection control
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#define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004)
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#define VREG_AND_CHIP_RESET_BOD_BITS _u(0x000000f1)
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#define VREG_AND_CHIP_RESET_BOD_RESET _u(0x00000091)
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_BOD_VSEL
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// Description : threshold select
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// 0000 - 0.473V
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// 0001 - 0.516V
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// 0010 - 0.559V
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// 0011 - 0.602V
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// 0100 - 0.645V
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// 0101 - 0.688V
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// 0110 - 0.731V
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// 0111 - 0.774V
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// 1000 - 0.817V
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// 1001 - 0.860V (default)
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// 1010 - 0.903V
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// 1011 - 0.946V
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// 1100 - 0.989V
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// 1101 - 1.032V
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// 1110 - 1.075V
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// 1111 - 1.118V
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#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _u(0x9)
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#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _u(0x000000f0)
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#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _u(7)
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#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _u(4)
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#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_BOD_EN
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// Description : enable
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// 0=not enabled, 1=enabled
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#define VREG_AND_CHIP_RESET_BOD_EN_RESET _u(0x1)
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#define VREG_AND_CHIP_RESET_BOD_EN_BITS _u(0x00000001)
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#define VREG_AND_CHIP_RESET_BOD_EN_MSB _u(0)
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#define VREG_AND_CHIP_RESET_BOD_EN_LSB _u(0)
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#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW"
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// =============================================================================
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// Register : VREG_AND_CHIP_RESET_CHIP_RESET
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// Description : Chip reset control and status
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#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _u(0x01110100)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG
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// Description : This is set by psm_restart from the debugger.
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// Its purpose is to branch bootcode to a safe mode when the
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// debugger has issued a psm_restart in order to recover from a
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// boot lock-up.
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// In the safe mode the debugger can repair the boot code, clear
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// this flag then reboot the processor.
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#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _u(0x0)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _u(0x01000000)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _u(24)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _u(24)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC"
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART
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// Description : Last reset was from the debug port
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _u(0x0)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _u(0x00100000)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _u(20)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _u(20)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN
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// Description : Last reset was from the RUN pin
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _u(0x0)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _u(0x00010000)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _u(16)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _u(16)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR
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// Description : Last reset was from the power-on reset or brown-out detection
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// blocks
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _u(0x0)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _u(0x00000100)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _u(8)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8)
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#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
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// =============================================================================
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#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
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