258 lines
13 KiB
C
258 lines
13 KiB
C
/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : SYSCFG
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// Version : 1
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// Bus type : apb
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// Description : Register block for various chip control signals
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// =============================================================================
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#ifndef HARDWARE_REGS_SYSCFG_DEFINED
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#define HARDWARE_REGS_SYSCFG_DEFINED
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// =============================================================================
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// Register : SYSCFG_PROC0_NMI_MASK
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// Description : Processor core 0 NMI source mask
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// Set a bit high to enable NMI from that IRQ
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#define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000)
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#define SYSCFG_PROC0_NMI_MASK_BITS _u(0xffffffff)
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#define SYSCFG_PROC0_NMI_MASK_RESET _u(0x00000000)
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#define SYSCFG_PROC0_NMI_MASK_MSB _u(31)
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#define SYSCFG_PROC0_NMI_MASK_LSB _u(0)
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#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW"
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// =============================================================================
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// Register : SYSCFG_PROC1_NMI_MASK
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// Description : Processor core 1 NMI source mask
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// Set a bit high to enable NMI from that IRQ
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#define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004)
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#define SYSCFG_PROC1_NMI_MASK_BITS _u(0xffffffff)
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#define SYSCFG_PROC1_NMI_MASK_RESET _u(0x00000000)
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#define SYSCFG_PROC1_NMI_MASK_MSB _u(31)
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#define SYSCFG_PROC1_NMI_MASK_LSB _u(0)
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#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW"
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// =============================================================================
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// Register : SYSCFG_PROC_CONFIG
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// Description : Configuration for processors
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#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008)
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#define SYSCFG_PROC_CONFIG_BITS _u(0xff000003)
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#define SYSCFG_PROC_CONFIG_RESET _u(0x10000000)
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID
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// Description : Configure proc1 DAP instance ID.
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// Recommend that this is NOT changed until you require debug
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// access in multi-chip environment
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// WARNING: do not set to 15 as this is reserved for RescueDP
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#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _u(0x1)
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#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _u(0xf0000000)
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#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _u(31)
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#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _u(28)
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#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID
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// Description : Configure proc0 DAP instance ID.
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// Recommend that this is NOT changed until you require debug
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// access in multi-chip environment
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// WARNING: do not set to 15 as this is reserved for RescueDP
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#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _u(0x0)
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#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _u(0x0f000000)
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#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _u(27)
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#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _u(24)
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#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
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// Description : Indication that proc1 has halted
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0)
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002)
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1)
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1)
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#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
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// Description : Indication that proc0 has halted
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0)
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001)
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0)
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0)
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#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
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// =============================================================================
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// Register : SYSCFG_PROC_IN_SYNC_BYPASS
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// Description : For each bit, if 1, bypass the input synchronizer between that
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// GPIO
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// and the GPIO input register in the SIO. The input synchronizers
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// should
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// generally be unbypassed, to avoid injecting metastabilities
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// into processors.
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// If you're feeling brave, you can bypass to save two cycles of
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// input
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// latency. This register applies to GPIO 0...29.
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#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0x3fffffff)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _u(29)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _u(0)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW"
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// =============================================================================
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// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
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// Description : For each bit, if 1, bypass the input synchronizer between that
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// GPIO
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// and the GPIO input register in the SIO. The input synchronizers
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// should
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// generally be unbypassed, to avoid injecting metastabilities
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// into processors.
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// If you're feeling brave, you can bypass to save two cycles of
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// input
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// latency. This register applies to GPIO 30...35 (the QSPI IOs).
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0x0000003f)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _u(5)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _u(0)
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#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW"
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// =============================================================================
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// Register : SYSCFG_DBGFORCE
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// Description : Directly control the SWD debug port of either processor
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#define SYSCFG_DBGFORCE_OFFSET _u(0x00000014)
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#define SYSCFG_DBGFORCE_BITS _u(0x000000ff)
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#define SYSCFG_DBGFORCE_RESET _u(0x00000066)
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_PROC1_ATTACH
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// Description : Attach processor 1 debug port to syscfg controls, and
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// disconnect it from external SWD pads.
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#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _u(0x0)
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#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _u(0x00000080)
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#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _u(7)
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#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _u(7)
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#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_PROC1_SWCLK
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// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
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#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _u(0x1)
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#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _u(0x00000040)
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#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _u(6)
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#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _u(6)
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#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_PROC1_SWDI
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// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
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#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _u(0x1)
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#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _u(0x00000020)
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#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _u(5)
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#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _u(5)
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#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_PROC1_SWDO
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// Description : Observe the value of processor 1 SWDIO output.
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#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-"
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#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _u(0x00000010)
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#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _u(4)
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#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _u(4)
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#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_PROC0_ATTACH
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// Description : Attach processor 0 debug port to syscfg controls, and
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// disconnect it from external SWD pads.
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#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _u(0x0)
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#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _u(0x00000008)
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#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _u(3)
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#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _u(3)
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#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_PROC0_SWCLK
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// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
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#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _u(0x1)
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#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _u(0x00000004)
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#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _u(2)
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#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _u(2)
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#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_PROC0_SWDI
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// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
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#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _u(0x1)
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#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _u(0x00000002)
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#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _u(1)
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#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _u(1)
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#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_DBGFORCE_PROC0_SWDO
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// Description : Observe the value of processor 0 SWDIO output.
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#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-"
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#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _u(0x00000001)
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#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _u(0)
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#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _u(0)
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#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO"
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// =============================================================================
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// Register : SYSCFG_MEMPOWERDOWN
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// Description : Control power downs to memories. Set high to power down
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// memories.
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// Use with extreme caution
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#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018)
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#define SYSCFG_MEMPOWERDOWN_BITS _u(0x000000ff)
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#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_ROM
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// Description : None
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#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080)
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#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7)
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#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(7)
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#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_USB
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// Description : None
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#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040)
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#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6)
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#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(6)
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#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM5
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// Description : None
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#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
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#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
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#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5)
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#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM4
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// Description : None
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#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
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#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
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#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4)
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#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM3
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// Description : None
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#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
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#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
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#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3)
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#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM2
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// Description : None
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#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
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#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
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#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2)
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#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM1
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// Description : None
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#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
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#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
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#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1)
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#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : SYSCFG_MEMPOWERDOWN_SRAM0
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// Description : None
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#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
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#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
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#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
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#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
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#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
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// =============================================================================
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#endif // HARDWARE_REGS_SYSCFG_DEFINED
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