136 lines
5.9 KiB
C
136 lines
5.9 KiB
C
/**
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* Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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// =============================================================================
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// Register block : PLL
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// Version : 1
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// Bus type : apb
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// Description : None
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// =============================================================================
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#ifndef HARDWARE_REGS_PLL_DEFINED
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#define HARDWARE_REGS_PLL_DEFINED
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// =============================================================================
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// Register : PLL_CS
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// Description : Control and Status
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// GENERAL CONSTRAINTS:
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// Reference clock frequency min=5MHz, max=800MHz
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// Feedback divider min=16, max=320
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// VCO frequency min=400MHz, max=1600MHz
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#define PLL_CS_OFFSET _u(0x00000000)
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#define PLL_CS_BITS _u(0x8000013f)
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#define PLL_CS_RESET _u(0x00000001)
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// -----------------------------------------------------------------------------
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// Field : PLL_CS_LOCK
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// Description : PLL is locked
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#define PLL_CS_LOCK_RESET _u(0x0)
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#define PLL_CS_LOCK_BITS _u(0x80000000)
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#define PLL_CS_LOCK_MSB _u(31)
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#define PLL_CS_LOCK_LSB _u(31)
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#define PLL_CS_LOCK_ACCESS "RO"
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// -----------------------------------------------------------------------------
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// Field : PLL_CS_BYPASS
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// Description : Passes the reference clock to the output instead of the divided
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// VCO. The VCO continues to run so the user can switch between
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// the reference clock and the divided VCO but the output will
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// glitch when doing so.
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#define PLL_CS_BYPASS_RESET _u(0x0)
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#define PLL_CS_BYPASS_BITS _u(0x00000100)
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#define PLL_CS_BYPASS_MSB _u(8)
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#define PLL_CS_BYPASS_LSB _u(8)
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#define PLL_CS_BYPASS_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PLL_CS_REFDIV
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// Description : Divides the PLL input reference clock.
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// Behaviour is undefined for div=0.
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// PLL output will be unpredictable during refdiv changes, wait
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// for lock=1 before using it.
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#define PLL_CS_REFDIV_RESET _u(0x01)
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#define PLL_CS_REFDIV_BITS _u(0x0000003f)
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#define PLL_CS_REFDIV_MSB _u(5)
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#define PLL_CS_REFDIV_LSB _u(0)
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#define PLL_CS_REFDIV_ACCESS "RW"
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// =============================================================================
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// Register : PLL_PWR
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// Description : Controls the PLL power modes.
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#define PLL_PWR_OFFSET _u(0x00000004)
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#define PLL_PWR_BITS _u(0x0000002d)
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#define PLL_PWR_RESET _u(0x0000002d)
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// -----------------------------------------------------------------------------
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// Field : PLL_PWR_VCOPD
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// Description : PLL VCO powerdown
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// To save power set high when PLL output not required or
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// bypass=1.
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#define PLL_PWR_VCOPD_RESET _u(0x1)
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#define PLL_PWR_VCOPD_BITS _u(0x00000020)
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#define PLL_PWR_VCOPD_MSB _u(5)
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#define PLL_PWR_VCOPD_LSB _u(5)
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#define PLL_PWR_VCOPD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PLL_PWR_POSTDIVPD
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// Description : PLL post divider powerdown
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// To save power set high when PLL output not required or
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// bypass=1.
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#define PLL_PWR_POSTDIVPD_RESET _u(0x1)
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#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008)
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#define PLL_PWR_POSTDIVPD_MSB _u(3)
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#define PLL_PWR_POSTDIVPD_LSB _u(3)
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#define PLL_PWR_POSTDIVPD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PLL_PWR_DSMPD
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// Description : PLL DSM powerdown
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// Nothing is achieved by setting this low.
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#define PLL_PWR_DSMPD_RESET _u(0x1)
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#define PLL_PWR_DSMPD_BITS _u(0x00000004)
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#define PLL_PWR_DSMPD_MSB _u(2)
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#define PLL_PWR_DSMPD_LSB _u(2)
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#define PLL_PWR_DSMPD_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PLL_PWR_PD
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// Description : PLL powerdown
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// To save power set high when PLL output not required.
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#define PLL_PWR_PD_RESET _u(0x1)
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#define PLL_PWR_PD_BITS _u(0x00000001)
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#define PLL_PWR_PD_MSB _u(0)
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#define PLL_PWR_PD_LSB _u(0)
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#define PLL_PWR_PD_ACCESS "RW"
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// =============================================================================
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// Register : PLL_FBDIV_INT
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// Description : Feedback divisor
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// (note: this PLL does not support fractional division)
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// see ctrl reg description for constraints
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#define PLL_FBDIV_INT_OFFSET _u(0x00000008)
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#define PLL_FBDIV_INT_BITS _u(0x00000fff)
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#define PLL_FBDIV_INT_RESET _u(0x00000000)
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#define PLL_FBDIV_INT_MSB _u(11)
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#define PLL_FBDIV_INT_LSB _u(0)
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#define PLL_FBDIV_INT_ACCESS "RW"
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// =============================================================================
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// Register : PLL_PRIM
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// Description : Controls the PLL post dividers for the primary output
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// (note: this PLL does not have a secondary output)
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// the primary output is driven from VCO divided by
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// postdiv1*postdiv2
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#define PLL_PRIM_OFFSET _u(0x0000000c)
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#define PLL_PRIM_BITS _u(0x00077000)
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#define PLL_PRIM_RESET _u(0x00077000)
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// -----------------------------------------------------------------------------
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// Field : PLL_PRIM_POSTDIV1
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// Description : divide by 1-7
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#define PLL_PRIM_POSTDIV1_RESET _u(0x7)
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#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000)
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#define PLL_PRIM_POSTDIV1_MSB _u(18)
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#define PLL_PRIM_POSTDIV1_LSB _u(16)
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#define PLL_PRIM_POSTDIV1_ACCESS "RW"
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// -----------------------------------------------------------------------------
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// Field : PLL_PRIM_POSTDIV2
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// Description : divide by 1-7
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#define PLL_PRIM_POSTDIV2_RESET _u(0x7)
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#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000)
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#define PLL_PRIM_POSTDIV2_MSB _u(14)
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#define PLL_PRIM_POSTDIV2_LSB _u(12)
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#define PLL_PRIM_POSTDIV2_ACCESS "RW"
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// =============================================================================
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#endif // HARDWARE_REGS_PLL_DEFINED
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