73 lines
3.9 KiB
C
73 lines
3.9 KiB
C
/**
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* \file
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*
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* \brief Instance description for QSPI
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_QSPI_INSTANCE_
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#define _SAMD51_QSPI_INSTANCE_
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/* ========== Register definition for QSPI peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_QSPI_CTRLA (0x42003400) /**< \brief (QSPI) Control A */
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#define REG_QSPI_CTRLB (0x42003404) /**< \brief (QSPI) Control B */
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#define REG_QSPI_BAUD (0x42003408) /**< \brief (QSPI) Baud Rate */
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#define REG_QSPI_RXDATA (0x4200340C) /**< \brief (QSPI) Receive Data */
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#define REG_QSPI_TXDATA (0x42003410) /**< \brief (QSPI) Transmit Data */
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#define REG_QSPI_INTENCLR (0x42003414) /**< \brief (QSPI) Interrupt Enable Clear */
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#define REG_QSPI_INTENSET (0x42003418) /**< \brief (QSPI) Interrupt Enable Set */
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#define REG_QSPI_INTFLAG (0x4200341C) /**< \brief (QSPI) Interrupt Flag Status and Clear */
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#define REG_QSPI_STATUS (0x42003420) /**< \brief (QSPI) Status Register */
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#define REG_QSPI_INSTRADDR (0x42003430) /**< \brief (QSPI) Instruction Address */
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#define REG_QSPI_INSTRCTRL (0x42003434) /**< \brief (QSPI) Instruction Code */
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#define REG_QSPI_INSTRFRAME (0x42003438) /**< \brief (QSPI) Instruction Frame */
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#define REG_QSPI_SCRAMBCTRL (0x42003440) /**< \brief (QSPI) Scrambling Mode */
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#define REG_QSPI_SCRAMBKEY (0x42003444) /**< \brief (QSPI) Scrambling Key */
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#else
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#define REG_QSPI_CTRLA (*(RwReg *)0x42003400UL) /**< \brief (QSPI) Control A */
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#define REG_QSPI_CTRLB (*(RwReg *)0x42003404UL) /**< \brief (QSPI) Control B */
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#define REG_QSPI_BAUD (*(RwReg *)0x42003408UL) /**< \brief (QSPI) Baud Rate */
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#define REG_QSPI_RXDATA (*(RoReg *)0x4200340CUL) /**< \brief (QSPI) Receive Data */
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#define REG_QSPI_TXDATA (*(WoReg *)0x42003410UL) /**< \brief (QSPI) Transmit Data */
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#define REG_QSPI_INTENCLR (*(RwReg *)0x42003414UL) /**< \brief (QSPI) Interrupt Enable Clear */
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#define REG_QSPI_INTENSET (*(RwReg *)0x42003418UL) /**< \brief (QSPI) Interrupt Enable Set */
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#define REG_QSPI_INTFLAG (*(RwReg *)0x4200341CUL) /**< \brief (QSPI) Interrupt Flag Status and Clear */
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#define REG_QSPI_STATUS (*(RoReg *)0x42003420UL) /**< \brief (QSPI) Status Register */
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#define REG_QSPI_INSTRADDR (*(RwReg *)0x42003430UL) /**< \brief (QSPI) Instruction Address */
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#define REG_QSPI_INSTRCTRL (*(RwReg *)0x42003434UL) /**< \brief (QSPI) Instruction Code */
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#define REG_QSPI_INSTRFRAME (*(RwReg *)0x42003438UL) /**< \brief (QSPI) Instruction Frame */
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#define REG_QSPI_SCRAMBCTRL (*(RwReg *)0x42003440UL) /**< \brief (QSPI) Scrambling Mode */
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#define REG_QSPI_SCRAMBKEY (*(WoReg *)0x42003444UL) /**< \brief (QSPI) Scrambling Key */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for QSPI peripheral ========== */
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#define QSPI_DMAC_ID_RX 83
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#define QSPI_DMAC_ID_TX 84
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#define QSPI_HADDR_MSB 23
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#define QSPI_OCMS 1
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#endif /* _SAMD51_QSPI_INSTANCE_ */
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