131 lines
9.2 KiB
C
131 lines
9.2 KiB
C
/**
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* \file
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*
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* \brief Instance description for OSCCTRL
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_OSCCTRL_INSTANCE_
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#define _SAMD51_OSCCTRL_INSTANCE_
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/* ========== Register definition for OSCCTRL peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_OSCCTRL_EVCTRL (0x40001000) /**< \brief (OSCCTRL) Event Control */
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#define REG_OSCCTRL_INTENCLR (0x40001004) /**< \brief (OSCCTRL) Interrupt Enable Clear */
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#define REG_OSCCTRL_INTENSET (0x40001008) /**< \brief (OSCCTRL) Interrupt Enable Set */
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#define REG_OSCCTRL_INTFLAG (0x4000100C) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
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#define REG_OSCCTRL_STATUS (0x40001010) /**< \brief (OSCCTRL) Status */
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#define REG_OSCCTRL_XOSCCTRL0 (0x40001014) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
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#define REG_OSCCTRL_XOSCCTRL1 (0x40001018) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
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#define REG_OSCCTRL_DFLLCTRLA (0x4000101C) /**< \brief (OSCCTRL) DFLL48M Control A */
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#define REG_OSCCTRL_DFLLCTRLB (0x40001020) /**< \brief (OSCCTRL) DFLL48M Control B */
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#define REG_OSCCTRL_DFLLVAL (0x40001024) /**< \brief (OSCCTRL) DFLL48M Value */
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#define REG_OSCCTRL_DFLLMUL (0x40001028) /**< \brief (OSCCTRL) DFLL48M Multiplier */
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#define REG_OSCCTRL_DFLLSYNC (0x4000102C) /**< \brief (OSCCTRL) DFLL48M Synchronization */
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#define REG_OSCCTRL_DPLLCTRLA0 (0x40001030) /**< \brief (OSCCTRL) DPLL Control A 0 */
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#define REG_OSCCTRL_DPLLRATIO0 (0x40001034) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
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#define REG_OSCCTRL_DPLLCTRLB0 (0x40001038) /**< \brief (OSCCTRL) DPLL Control B 0 */
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#define REG_OSCCTRL_DPLLSYNCBUSY0 (0x4000103C) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
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#define REG_OSCCTRL_DPLLSTATUS0 (0x40001040) /**< \brief (OSCCTRL) DPLL Status 0 */
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#define REG_OSCCTRL_DPLLCTRLA1 (0x40001044) /**< \brief (OSCCTRL) DPLL Control A 1 */
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#define REG_OSCCTRL_DPLLRATIO1 (0x40001048) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
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#define REG_OSCCTRL_DPLLCTRLB1 (0x4000104C) /**< \brief (OSCCTRL) DPLL Control B 1 */
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#define REG_OSCCTRL_DPLLSYNCBUSY1 (0x40001050) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
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#define REG_OSCCTRL_DPLLSTATUS1 (0x40001054) /**< \brief (OSCCTRL) DPLL Status 1 */
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#else
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#define REG_OSCCTRL_EVCTRL (*(RwReg8 *)0x40001000UL) /**< \brief (OSCCTRL) Event Control */
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#define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40001004UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
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#define REG_OSCCTRL_INTENSET (*(RwReg *)0x40001008UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
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#define REG_OSCCTRL_INTFLAG (*(RwReg *)0x4000100CUL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
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#define REG_OSCCTRL_STATUS (*(RoReg *)0x40001010UL) /**< \brief (OSCCTRL) Status */
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#define REG_OSCCTRL_XOSCCTRL0 (*(RwReg *)0x40001014UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 0 */
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#define REG_OSCCTRL_XOSCCTRL1 (*(RwReg *)0x40001018UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator Control 1 */
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#define REG_OSCCTRL_DFLLCTRLA (*(RwReg8 *)0x4000101CUL) /**< \brief (OSCCTRL) DFLL48M Control A */
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#define REG_OSCCTRL_DFLLCTRLB (*(RwReg8 *)0x40001020UL) /**< \brief (OSCCTRL) DFLL48M Control B */
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#define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40001024UL) /**< \brief (OSCCTRL) DFLL48M Value */
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#define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40001028UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */
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#define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x4000102CUL) /**< \brief (OSCCTRL) DFLL48M Synchronization */
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#define REG_OSCCTRL_DPLLCTRLA0 (*(RwReg8 *)0x40001030UL) /**< \brief (OSCCTRL) DPLL Control A 0 */
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#define REG_OSCCTRL_DPLLRATIO0 (*(RwReg *)0x40001034UL) /**< \brief (OSCCTRL) DPLL Ratio Control 0 */
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#define REG_OSCCTRL_DPLLCTRLB0 (*(RwReg *)0x40001038UL) /**< \brief (OSCCTRL) DPLL Control B 0 */
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#define REG_OSCCTRL_DPLLSYNCBUSY0 (*(RoReg *)0x4000103CUL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 0 */
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#define REG_OSCCTRL_DPLLSTATUS0 (*(RoReg *)0x40001040UL) /**< \brief (OSCCTRL) DPLL Status 0 */
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#define REG_OSCCTRL_DPLLCTRLA1 (*(RwReg8 *)0x40001044UL) /**< \brief (OSCCTRL) DPLL Control A 1 */
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#define REG_OSCCTRL_DPLLRATIO1 (*(RwReg *)0x40001048UL) /**< \brief (OSCCTRL) DPLL Ratio Control 1 */
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#define REG_OSCCTRL_DPLLCTRLB1 (*(RwReg *)0x4000104CUL) /**< \brief (OSCCTRL) DPLL Control B 1 */
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#define REG_OSCCTRL_DPLLSYNCBUSY1 (*(RoReg *)0x40001050UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy 1 */
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#define REG_OSCCTRL_DPLLSTATUS1 (*(RoReg *)0x40001054UL) /**< \brief (OSCCTRL) DPLL Status 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for OSCCTRL peripheral ========== */
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#define OSCCTRL_DFLLS_NUM 1 // Number of DFLLs
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#define OSCCTRL_DFLL_IMPLEMENTED 1 // DFLL implemented
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#define OSCCTRL_DFLL48M_BIASTESTPT_IMPLEMENTED 0 // DFLL48M bias test mode implemented
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#define OSCCTRL_DFLL48M_CDACSTEPSIZE_SIZE 2 // Size COARSE DAC STEP
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#define OSCCTRL_DFLL48M_COARSE_RESET_VALUE 32 // DFLL48M Frequency Coarse Reset Value (Before Calibration)
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#define OSCCTRL_DFLL48M_COARSE_SIZE 6 // Size COARSE CALIBRATION
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#define OSCCTRL_DFLL48M_ENABLE_RESET_VALUE 1 // Run oscillator at reset
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#define OSCCTRL_DFLL48M_FDACSTEPSIZE_SIZE 2 // Size FINE DAC STEP
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#define OSCCTRL_DFLL48M_FINE_RESET_VALUE 128 // DFLL48M Frequency Fine Reset Value (Before Calibration)
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#define OSCCTRL_DFLL48M_FINE_SIZE 8 // Size FINE CALIBRATION
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#define OSCCTRL_DFLL48M_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
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#define OSCCTRL_DFLL48M_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
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#define OSCCTRL_DFLL48M_TCAL_SIZE 4 // Size TEMP CALIBRATION
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#define OSCCTRL_DFLL48M_TCBIAS_SIZE 2 // Size TC BIAS CALIBRATION
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#define OSCCTRL_DFLL48M_TESTPTSEL_SIZE 3 // Size TEST POINT SELECTOR
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#define OSCCTRL_DFLL48M_WAITLOCK_ACTIVE 1 // Enable Wait Lock Feature
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#define OSCCTRL_DPLLS_NUM 2 // Number of DPLLs
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#define OSCCTRL_DPLL0_IMPLEMENTED 1 // DPLL0 implemented
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#define OSCCTRL_DPLL0_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
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#define OSCCTRL_DPLL0_OCC_IMPLEMENTED 1 // DPLL0 OCC Implemented
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#define OSCCTRL_DPLL1_IMPLEMENTED 1 // DPLL1 implemented
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#define OSCCTRL_DPLL1_I12ND_I12NDFRAC_PAD_CONTROL 0 // NOT_IMPLEMENTED: The ND and NDFRAC pad tests are not used, use registers instead
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#define OSCCTRL_DPLL1_OCC_IMPLEMENTED 0 // DPLL1 OCC Implemented
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#define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
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#define OSCCTRL_GCLK_ID_FDPLL0 1 // Index of Generic Clock for DPLL0
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#define OSCCTRL_GCLK_ID_FDPLL1 2 // Index of Generic Clock for DPLL1
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#define OSCCTRL_GCLK_ID_FDPLL032K 3 // Index of Generic Clock for DPLL0 32K
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#define OSCCTRL_GCLK_ID_FDPLL132K 3 // Index of Generic Clock for DPLL1 32K
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#define OSCCTRL_OSC16M_IMPLEMENTED 0 // OSC16M implemented
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#define OSCCTRL_OSC48M_IMPLEMENTED 0 // OSC48M implemented
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#define OSCCTRL_OSC48M_NUM 1
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#define OSCCTRL_RCOSCS_NUM 1 // Number of RCOSCs (min 1)
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#define OSCCTRL_XOSCS_NUM 2 // Number of XOSCs
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#define OSCCTRL_XOSC0_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
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#define OSCCTRL_XOSC0_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
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#define OSCCTRL_XOSC0_IMPLEMENTED 1 // XOSC0 implemented
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#define OSCCTRL_XOSC0_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
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#define OSCCTRL_XOSC0_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
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#define OSCCTRL_XOSC1_CFD_CLK_SELECT_SIZE 4 // Clock fail prescaler size
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#define OSCCTRL_XOSC1_CFD_IMPLEMENTED 1 // Clock fail detected for xosc implemented
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#define OSCCTRL_XOSC1_IMPLEMENTED 1 // XOSC1 implemented
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#define OSCCTRL_XOSC1_ONDEMAND_RESET_VALUE 1 // Run oscillator always or only when requested
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#define OSCCTRL_XOSC1_RUNSTDBY_RESET_VALUE 0 // Run oscillator even if standby mode
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#define OSCCTRL_DFLL48M_VERSION 0x100
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#define OSCCTRL_FDPLL_VERSION 0x100
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#define OSCCTRL_XOSC_VERSION 0x100
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#endif /* _SAMD51_OSCCTRL_INSTANCE_ */
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