60 lines
3.3 KiB
C
60 lines
3.3 KiB
C
/**
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* \file
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*
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* \brief Instance description for OSC32KCTRL
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD51_OSC32KCTRL_INSTANCE_
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#define _SAMD51_OSC32KCTRL_INSTANCE_
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/* ========== Register definition for OSC32KCTRL peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_OSC32KCTRL_INTENCLR (0x40001400) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
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#define REG_OSC32KCTRL_INTENSET (0x40001404) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
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#define REG_OSC32KCTRL_INTFLAG (0x40001408) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
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#define REG_OSC32KCTRL_STATUS (0x4000140C) /**< \brief (OSC32KCTRL) Power and Clocks Status */
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#define REG_OSC32KCTRL_RTCCTRL (0x40001410) /**< \brief (OSC32KCTRL) RTC Clock Selection */
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#define REG_OSC32KCTRL_XOSC32K (0x40001414) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
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#define REG_OSC32KCTRL_CFDCTRL (0x40001416) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
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#define REG_OSC32KCTRL_EVCTRL (0x40001417) /**< \brief (OSC32KCTRL) Event Control */
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#define REG_OSC32KCTRL_OSCULP32K (0x4000141C) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
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#else
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#define REG_OSC32KCTRL_INTENCLR (*(RwReg *)0x40001400UL) /**< \brief (OSC32KCTRL) Interrupt Enable Clear */
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#define REG_OSC32KCTRL_INTENSET (*(RwReg *)0x40001404UL) /**< \brief (OSC32KCTRL) Interrupt Enable Set */
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#define REG_OSC32KCTRL_INTFLAG (*(RwReg *)0x40001408UL) /**< \brief (OSC32KCTRL) Interrupt Flag Status and Clear */
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#define REG_OSC32KCTRL_STATUS (*(RoReg *)0x4000140CUL) /**< \brief (OSC32KCTRL) Power and Clocks Status */
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#define REG_OSC32KCTRL_RTCCTRL (*(RwReg8 *)0x40001410UL) /**< \brief (OSC32KCTRL) RTC Clock Selection */
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#define REG_OSC32KCTRL_XOSC32K (*(RwReg16*)0x40001414UL) /**< \brief (OSC32KCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
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#define REG_OSC32KCTRL_CFDCTRL (*(RwReg8 *)0x40001416UL) /**< \brief (OSC32KCTRL) Clock Failure Detector Control */
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#define REG_OSC32KCTRL_EVCTRL (*(RwReg8 *)0x40001417UL) /**< \brief (OSC32KCTRL) Event Control */
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#define REG_OSC32KCTRL_OSCULP32K (*(RwReg *)0x4000141CUL) /**< \brief (OSC32KCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for OSC32KCTRL peripheral ========== */
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#define OSC32KCTRL_OSC32K_COARSE_CALIB_MSB 0 // OSC32K coarse calibration size
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#endif /* _SAMD51_OSC32KCTRL_INSTANCE_ */
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