59 lines
4.9 KiB
C
59 lines
4.9 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4S_CMCC_INSTANCE_
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#define _SAM4S_CMCC_INSTANCE_
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/* ========== Register definition for CMCC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_CMCC_TYPE (0x4007C000U) /**< \brief (CMCC) Cache Controller Type Register */
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#define REG_CMCC_CFG (0x4007C004U) /**< \brief (CMCC) Cache Controller Configuration Register */
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#define REG_CMCC_CTRL (0x4007C008U) /**< \brief (CMCC) Cache Controller Control Register */
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#define REG_CMCC_SR (0x4007C00CU) /**< \brief (CMCC) Cache Controller Status Register */
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#define REG_CMCC_MAINT0 (0x4007C020U) /**< \brief (CMCC) Cache Controller Maintenance Register 0 */
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#define REG_CMCC_MAINT1 (0x4007C024U) /**< \brief (CMCC) Cache Controller Maintenance Register 1 */
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#define REG_CMCC_MCFG (0x4007C028U) /**< \brief (CMCC) Cache Controller Monitor Configuration Register */
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#define REG_CMCC_MEN (0x4007C02CU) /**< \brief (CMCC) Cache Controller Monitor Enable Register */
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#define REG_CMCC_MCTRL (0x4007C030U) /**< \brief (CMCC) Cache Controller Monitor Control Register */
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#define REG_CMCC_MSR (0x4007C034U) /**< \brief (CMCC) Cache Controller Monitor Status Register */
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#else
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#define REG_CMCC_TYPE (*(__I uint32_t*)0x4007C000U) /**< \brief (CMCC) Cache Controller Type Register */
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#define REG_CMCC_CFG (*(__IO uint32_t*)0x4007C004U) /**< \brief (CMCC) Cache Controller Configuration Register */
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#define REG_CMCC_CTRL (*(__O uint32_t*)0x4007C008U) /**< \brief (CMCC) Cache Controller Control Register */
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#define REG_CMCC_SR (*(__I uint32_t*)0x4007C00CU) /**< \brief (CMCC) Cache Controller Status Register */
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#define REG_CMCC_MAINT0 (*(__O uint32_t*)0x4007C020U) /**< \brief (CMCC) Cache Controller Maintenance Register 0 */
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#define REG_CMCC_MAINT1 (*(__O uint32_t*)0x4007C024U) /**< \brief (CMCC) Cache Controller Maintenance Register 1 */
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#define REG_CMCC_MCFG (*(__IO uint32_t*)0x4007C028U) /**< \brief (CMCC) Cache Controller Monitor Configuration Register */
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#define REG_CMCC_MEN (*(__IO uint32_t*)0x4007C02CU) /**< \brief (CMCC) Cache Controller Monitor Enable Register */
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#define REG_CMCC_MCTRL (*(__O uint32_t*)0x4007C030U) /**< \brief (CMCC) Cache Controller Monitor Control Register */
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#define REG_CMCC_MSR (*(__I uint32_t*)0x4007C034U) /**< \brief (CMCC) Cache Controller Monitor Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4S_CMCC_INSTANCE_ */
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