81 lines
5.6 KiB
C
81 lines
5.6 KiB
C
/* ----------------------------------------------------------------------------
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* SAM Software Package License
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* ----------------------------------------------------------------------------
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* Copyright (c) 2012, Atmel Corporation
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following condition is met:
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*
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* - Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the disclaimer below.
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*
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* Atmel's name may not be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* ----------------------------------------------------------------------------
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*/
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#ifndef _SAM3XA_TWI0_INSTANCE_
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#define _SAM3XA_TWI0_INSTANCE_
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/* ========== Register definition for TWI0 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TWI0_CR (0x4008C000U) /**< \brief (TWI0) Control Register */
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#define REG_TWI0_MMR (0x4008C004U) /**< \brief (TWI0) Master Mode Register */
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#define REG_TWI0_SMR (0x4008C008U) /**< \brief (TWI0) Slave Mode Register */
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#define REG_TWI0_IADR (0x4008C00CU) /**< \brief (TWI0) Internal Address Register */
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#define REG_TWI0_CWGR (0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */
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#define REG_TWI0_SR (0x4008C020U) /**< \brief (TWI0) Status Register */
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#define REG_TWI0_IER (0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */
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#define REG_TWI0_IDR (0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */
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#define REG_TWI0_IMR (0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */
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#define REG_TWI0_RHR (0x4008C030U) /**< \brief (TWI0) Receive Holding Register */
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#define REG_TWI0_THR (0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */
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#define REG_TWI0_RPR (0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */
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#define REG_TWI0_RCR (0x4008C104U) /**< \brief (TWI0) Receive Counter Register */
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#define REG_TWI0_TPR (0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */
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#define REG_TWI0_TCR (0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */
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#define REG_TWI0_RNPR (0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */
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#define REG_TWI0_RNCR (0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */
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#define REG_TWI0_TNPR (0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */
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#define REG_TWI0_TNCR (0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */
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#define REG_TWI0_PTCR (0x4008C120U) /**< \brief (TWI0) Transfer Control Register */
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#define REG_TWI0_PTSR (0x4008C124U) /**< \brief (TWI0) Transfer Status Register */
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#else
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#define REG_TWI0_CR (*(WoReg*)0x4008C000U) /**< \brief (TWI0) Control Register */
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#define REG_TWI0_MMR (*(RwReg*)0x4008C004U) /**< \brief (TWI0) Master Mode Register */
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#define REG_TWI0_SMR (*(RwReg*)0x4008C008U) /**< \brief (TWI0) Slave Mode Register */
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#define REG_TWI0_IADR (*(RwReg*)0x4008C00CU) /**< \brief (TWI0) Internal Address Register */
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#define REG_TWI0_CWGR (*(RwReg*)0x4008C010U) /**< \brief (TWI0) Clock Waveform Generator Register */
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#define REG_TWI0_SR (*(RoReg*)0x4008C020U) /**< \brief (TWI0) Status Register */
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#define REG_TWI0_IER (*(WoReg*)0x4008C024U) /**< \brief (TWI0) Interrupt Enable Register */
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#define REG_TWI0_IDR (*(WoReg*)0x4008C028U) /**< \brief (TWI0) Interrupt Disable Register */
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#define REG_TWI0_IMR (*(RoReg*)0x4008C02CU) /**< \brief (TWI0) Interrupt Mask Register */
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#define REG_TWI0_RHR (*(RoReg*)0x4008C030U) /**< \brief (TWI0) Receive Holding Register */
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#define REG_TWI0_THR (*(WoReg*)0x4008C034U) /**< \brief (TWI0) Transmit Holding Register */
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#define REG_TWI0_RPR (*(RwReg*)0x4008C100U) /**< \brief (TWI0) Receive Pointer Register */
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#define REG_TWI0_RCR (*(RwReg*)0x4008C104U) /**< \brief (TWI0) Receive Counter Register */
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#define REG_TWI0_TPR (*(RwReg*)0x4008C108U) /**< \brief (TWI0) Transmit Pointer Register */
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#define REG_TWI0_TCR (*(RwReg*)0x4008C10CU) /**< \brief (TWI0) Transmit Counter Register */
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#define REG_TWI0_RNPR (*(RwReg*)0x4008C110U) /**< \brief (TWI0) Receive Next Pointer Register */
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#define REG_TWI0_RNCR (*(RwReg*)0x4008C114U) /**< \brief (TWI0) Receive Next Counter Register */
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#define REG_TWI0_TNPR (*(RwReg*)0x4008C118U) /**< \brief (TWI0) Transmit Next Pointer Register */
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#define REG_TWI0_TNCR (*(RwReg*)0x4008C11CU) /**< \brief (TWI0) Transmit Next Counter Register */
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#define REG_TWI0_PTCR (*(WoReg*)0x4008C120U) /**< \brief (TWI0) Transfer Control Register */
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#define REG_TWI0_PTSR (*(RoReg*)0x4008C124U) /**< \brief (TWI0) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3XA_TWI0_INSTANCE_ */
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