98 lines
6.0 KiB
C
98 lines
6.0 KiB
C
/**
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* \file
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*
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* \brief Instance description for TC5
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_TC5_INSTANCE_
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#define _SAMD21_TC5_INSTANCE_
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/* ========== Register definition for TC5 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TC5_CTRLA (0x42003400) /**< \brief (TC5) Control A */
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#define REG_TC5_READREQ (0x42003402) /**< \brief (TC5) Read Request */
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#define REG_TC5_CTRLBCLR (0x42003404) /**< \brief (TC5) Control B Clear */
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#define REG_TC5_CTRLBSET (0x42003405) /**< \brief (TC5) Control B Set */
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#define REG_TC5_CTRLC (0x42003406) /**< \brief (TC5) Control C */
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#define REG_TC5_DBGCTRL (0x42003408) /**< \brief (TC5) Debug Control */
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#define REG_TC5_EVCTRL (0x4200340A) /**< \brief (TC5) Event Control */
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#define REG_TC5_INTENCLR (0x4200340C) /**< \brief (TC5) Interrupt Enable Clear */
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#define REG_TC5_INTENSET (0x4200340D) /**< \brief (TC5) Interrupt Enable Set */
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#define REG_TC5_INTFLAG (0x4200340E) /**< \brief (TC5) Interrupt Flag Status and Clear */
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#define REG_TC5_STATUS (0x4200340F) /**< \brief (TC5) Status */
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#define REG_TC5_COUNT16_COUNT (0x42003410) /**< \brief (TC5) COUNT16 Counter Value */
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#define REG_TC5_COUNT16_CC0 (0x42003418) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
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#define REG_TC5_COUNT16_CC1 (0x4200341A) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
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#define REG_TC5_COUNT32_COUNT (0x42003410) /**< \brief (TC5) COUNT32 Counter Value */
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#define REG_TC5_COUNT32_CC0 (0x42003418) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
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#define REG_TC5_COUNT32_CC1 (0x4200341C) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
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#define REG_TC5_COUNT8_COUNT (0x42003410) /**< \brief (TC5) COUNT8 Counter Value */
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#define REG_TC5_COUNT8_PER (0x42003414) /**< \brief (TC5) COUNT8 Period Value */
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#define REG_TC5_COUNT8_CC0 (0x42003418) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
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#define REG_TC5_COUNT8_CC1 (0x42003419) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
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#else
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#define REG_TC5_CTRLA (*(RwReg16*)0x42003400UL) /**< \brief (TC5) Control A */
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#define REG_TC5_READREQ (*(RwReg16*)0x42003402UL) /**< \brief (TC5) Read Request */
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#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404UL) /**< \brief (TC5) Control B Clear */
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#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405UL) /**< \brief (TC5) Control B Set */
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#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406UL) /**< \brief (TC5) Control C */
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#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408UL) /**< \brief (TC5) Debug Control */
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#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AUL) /**< \brief (TC5) Event Control */
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#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CUL) /**< \brief (TC5) Interrupt Enable Clear */
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#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DUL) /**< \brief (TC5) Interrupt Enable Set */
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#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EUL) /**< \brief (TC5) Interrupt Flag Status and Clear */
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#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FUL) /**< \brief (TC5) Status */
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#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410UL) /**< \brief (TC5) COUNT16 Counter Value */
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#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418UL) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
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#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AUL) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
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#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410UL) /**< \brief (TC5) COUNT32 Counter Value */
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#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418UL) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
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#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CUL) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
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#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410UL) /**< \brief (TC5) COUNT8 Counter Value */
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#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414UL) /**< \brief (TC5) COUNT8 Period Value */
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#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418UL) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
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#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419UL) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TC5 peripheral ========== */
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#define TC5_CC8_NUM 2 // Number of 8-bit Counters
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#define TC5_CC16_NUM 2 // Number of 16-bit Counters
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#define TC5_CC32_NUM 2 // Number of 32-bit Counters
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#define TC5_DITHERING_EXT 0 // Dithering feature implemented
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#define TC5_DMAC_ID_MC_0 31
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#define TC5_DMAC_ID_MC_1 32
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#define TC5_DMAC_ID_MC_LSB 31
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#define TC5_DMAC_ID_MC_MSB 32
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#define TC5_DMAC_ID_MC_SIZE 2
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#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
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#define TC5_GCLK_ID 28 // Index of Generic Clock
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#define TC5_MASTER 0
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#define TC5_OW_NUM 2 // Number of Output Waveforms
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#define TC5_PERIOD_EXT 0 // Period feature implemented
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#define TC5_SHADOW_EXT 0 // Shadow feature implemented
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#endif /* _SAMD21_TC5_INSTANCE_ */
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