80 lines
4.1 KiB
C
80 lines
4.1 KiB
C
/**
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* \file
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*
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* \brief Instance description for SPI1
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_SPI1_INSTANCE_H_
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#define _SAME70_SPI1_INSTANCE_H_
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/* ========== Register definition for SPI1 peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SPI1_CR (0x40058000) /**< (SPI1) Control Register */
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#define REG_SPI1_MR (0x40058004) /**< (SPI1) Mode Register */
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#define REG_SPI1_RDR (0x40058008) /**< (SPI1) Receive Data Register */
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#define REG_SPI1_TDR (0x4005800C) /**< (SPI1) Transmit Data Register */
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#define REG_SPI1_SR (0x40058010) /**< (SPI1) Status Register */
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#define REG_SPI1_IER (0x40058014) /**< (SPI1) Interrupt Enable Register */
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#define REG_SPI1_IDR (0x40058018) /**< (SPI1) Interrupt Disable Register */
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#define REG_SPI1_IMR (0x4005801C) /**< (SPI1) Interrupt Mask Register */
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#define REG_SPI1_CSR (0x40058030) /**< (SPI1) Chip Select Register */
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#define REG_SPI1_CSR0 (0x40058030) /**< (SPI1) Chip Select Register 0 */
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#define REG_SPI1_CSR1 (0x40058034) /**< (SPI1) Chip Select Register 1 */
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#define REG_SPI1_CSR2 (0x40058038) /**< (SPI1) Chip Select Register 2 */
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#define REG_SPI1_CSR3 (0x4005803C) /**< (SPI1) Chip Select Register 3 */
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#define REG_SPI1_WPMR (0x400580E4) /**< (SPI1) Write Protection Mode Register */
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#define REG_SPI1_WPSR (0x400580E8) /**< (SPI1) Write Protection Status Register */
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#else
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#define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< (SPI1) Control Register */
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#define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< (SPI1) Mode Register */
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#define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< (SPI1) Receive Data Register */
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#define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< (SPI1) Transmit Data Register */
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#define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< (SPI1) Status Register */
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#define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< (SPI1) Interrupt Enable Register */
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#define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< (SPI1) Interrupt Disable Register */
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#define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< (SPI1) Interrupt Mask Register */
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#define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register */
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#define REG_SPI1_CSR0 (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register 0 */
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#define REG_SPI1_CSR1 (*(__IO uint32_t*)0x40058034U) /**< (SPI1) Chip Select Register 1 */
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#define REG_SPI1_CSR2 (*(__IO uint32_t*)0x40058038U) /**< (SPI1) Chip Select Register 2 */
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#define REG_SPI1_CSR3 (*(__IO uint32_t*)0x4005803CU) /**< (SPI1) Chip Select Register 3 */
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#define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< (SPI1) Write Protection Mode Register */
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#define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< (SPI1) Write Protection Status Register */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for SPI1 peripheral ========== */
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#define SPI1_DMAC_ID_RX 4
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#define SPI1_DMAC_ID_TX 3
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#define SPI1_INSTANCE_ID 42
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#define SPI1_CLOCK_ID 42
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#endif /* _SAME70_SPI1_INSTANCE_ */
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