72 lines
3.4 KiB
C
72 lines
3.4 KiB
C
/**
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* \file
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*
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* \brief Instance description for I2SC0
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_I2SC0_INSTANCE_H_
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#define _SAME70_I2SC0_INSTANCE_H_
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/* ========== Register definition for I2SC0 peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_I2SC0_CR (0x4008C000) /**< (I2SC0) Control Register */
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#define REG_I2SC0_MR (0x4008C004) /**< (I2SC0) Mode Register */
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#define REG_I2SC0_SR (0x4008C008) /**< (I2SC0) Status Register */
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#define REG_I2SC0_SCR (0x4008C00C) /**< (I2SC0) Status Clear Register */
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#define REG_I2SC0_SSR (0x4008C010) /**< (I2SC0) Status Set Register */
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#define REG_I2SC0_IER (0x4008C014) /**< (I2SC0) Interrupt Enable Register */
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#define REG_I2SC0_IDR (0x4008C018) /**< (I2SC0) Interrupt Disable Register */
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#define REG_I2SC0_IMR (0x4008C01C) /**< (I2SC0) Interrupt Mask Register */
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#define REG_I2SC0_RHR (0x4008C020) /**< (I2SC0) Receiver Holding Register */
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#define REG_I2SC0_THR (0x4008C024) /**< (I2SC0) Transmitter Holding Register */
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#else
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#define REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) /**< (I2SC0) Control Register */
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#define REG_I2SC0_MR (*(__IO uint32_t*)0x4008C004U) /**< (I2SC0) Mode Register */
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#define REG_I2SC0_SR (*(__I uint32_t*)0x4008C008U) /**< (I2SC0) Status Register */
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#define REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) /**< (I2SC0) Status Clear Register */
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#define REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) /**< (I2SC0) Status Set Register */
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#define REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) /**< (I2SC0) Interrupt Enable Register */
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#define REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) /**< (I2SC0) Interrupt Disable Register */
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#define REG_I2SC0_IMR (*(__I uint32_t*)0x4008C01CU) /**< (I2SC0) Interrupt Mask Register */
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#define REG_I2SC0_RHR (*(__I uint32_t*)0x4008C020U) /**< (I2SC0) Receiver Holding Register */
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#define REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) /**< (I2SC0) Transmitter Holding Register */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for I2SC0 peripheral ========== */
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#define I2SC0_INSTANCE_ID 69
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#define I2SC0_CLOCK_ID 69
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#define I2SC0_DMAC_ID_TX_LEFT 44
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#define I2SC0_DMAC_ID_RX_LEFT 45
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#define I2SC0_DMAC_ID_TX_RIGHT 48
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#define I2SC0_DMAC_ID_RX_RIGHT 49
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#endif /* _SAME70_I2SC0_INSTANCE_ */
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