568 lines
24 KiB
C
568 lines
24 KiB
C
/**
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******************************************************************************
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* @file stm32f0xx_ll_adc.c
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* @author MCD Application Team
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* @brief ADC LL module driver
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx_ll_adc.h"
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#include "stm32f0xx_ll_bus.h"
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#ifdef USE_FULL_ASSERT
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#include "stm32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif
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/** @addtogroup STM32F0xx_LL_Driver
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* @{
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*/
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#if defined (ADC1)
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/** @addtogroup ADC_LL ADC
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @addtogroup ADC_LL_Private_Constants
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* @{
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*/
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/* Definitions of ADC hardware constraints delays */
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/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
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/* not timeout values: */
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/* Timeout values for ADC operations are dependent to device clock */
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/* configuration (system clock versus ADC clock), */
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/* and therefore must be defined in user application. */
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/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
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/* values definition. */
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/* Note: ADC timeout values are defined here in CPU cycles to be independent */
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/* of device clock setting. */
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/* In user application, ADC timeout values should be defined with */
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/* temporal values, in function of device clock settings. */
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/* Highest ratio CPU clock frequency vs ADC clock frequency: */
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/* - ADC clock from synchronous clock with AHB prescaler 512, */
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/* APB prescaler 16, ADC prescaler 4. */
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/* - ADC clock from asynchronous clock (HSI) with prescaler 1, */
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/* with highest ratio CPU clock frequency vs HSI clock frequency: */
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/* CPU clock frequency max 48MHz, HSI frequency 14MHz: ratio 4. */
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/* Unit: CPU cycles. */
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#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
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#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
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#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup ADC_LL_Private_Macros
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* @{
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*/
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/* Check of parameters for configuration of ADC hierarchical scope: */
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/* common to several ADC instances. */
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/* Check of parameters for configuration of ADC hierarchical scope: */
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/* ADC instance. */
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#define IS_LL_ADC_CLOCK(__CLOCK__) \
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( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
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|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
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|| ((__CLOCK__) == LL_ADC_CLOCK_ASYNC) \
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)
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#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
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( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
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|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
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|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
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|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
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)
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#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
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( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
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|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
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)
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#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
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( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
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|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
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|| ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF) \
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|| ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF) \
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)
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/* Check of parameters for configuration of ADC hierarchical scope: */
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/* ADC group regular */
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#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
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( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
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|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
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|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \
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|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
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|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
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|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
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)
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#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
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( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
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|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
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)
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#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
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( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
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|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
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|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
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)
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#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
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( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
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|| ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
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)
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#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
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( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
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|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
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)
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup ADC_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup ADC_LL_EF_Init
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* @{
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*/
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/**
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* @brief De-initialize registers of all ADC instances belonging to
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* the same ADC common instance to their default reset values.
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* @note This function is performing a hard reset, using high level
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* clock source RCC ADC reset.
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* @param ADCxy_COMMON ADC common instance
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* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: ADC common registers are de-initialized
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* - ERROR: not applicable
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*/
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ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
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{
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/* Check the parameters */
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assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
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/* Force reset of ADC clock (core clock) */
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LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1);
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/* Release reset of ADC clock (core clock) */
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LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1);
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return SUCCESS;
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}
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/**
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* @brief De-initialize registers of the selected ADC instance
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* to their default reset values.
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* @note To reset all ADC instances quickly (perform a hard reset),
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* use function @ref LL_ADC_CommonDeInit().
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* @note If this functions returns error status, it means that ADC instance
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* is in an unknown state.
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* In this case, perform a hard reset using high level
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* clock source RCC ADC reset.
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* Refer to function @ref LL_ADC_CommonDeInit().
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* @param ADCx ADC instance
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: ADC registers are de-initialized
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* - ERROR: ADC registers are not de-initialized
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*/
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ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
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{
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ErrorStatus status = SUCCESS;
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__IO uint32_t timeout_cpu_cycles = 0U;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(ADCx));
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/* Disable ADC instance if not already disabled. */
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if(LL_ADC_IsEnabled(ADCx) == 1U)
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{
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/* Set ADC group regular trigger source to SW start to ensure to not */
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/* have an external trigger event occurring during the conversion stop */
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/* ADC disable process. */
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LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
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/* Stop potential ADC conversion on going on ADC group regular. */
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if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
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{
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if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
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{
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LL_ADC_REG_StopConversion(ADCx);
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}
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}
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/* Wait for ADC conversions are effectively stopped */
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timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
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while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U)
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{
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if(timeout_cpu_cycles-- == 0U)
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{
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/* Time-out error */
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status = ERROR;
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}
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}
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/* Disable the ADC instance */
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LL_ADC_Disable(ADCx);
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/* Wait for ADC instance is effectively disabled */
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timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
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while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
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{
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if(timeout_cpu_cycles-- == 0U)
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{
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/* Time-out error */
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status = ERROR;
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}
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}
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}
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/* Check whether ADC state is compliant with expected state */
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if(READ_BIT(ADCx->CR,
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( ADC_CR_ADSTP | ADC_CR_ADSTART
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| ADC_CR_ADDIS | ADC_CR_ADEN )
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)
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== 0U)
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{
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/* ========== Reset ADC registers ========== */
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/* Reset register IER */
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CLEAR_BIT(ADCx->IER,
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( LL_ADC_IT_ADRDY
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| LL_ADC_IT_EOC
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| LL_ADC_IT_EOS
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| LL_ADC_IT_OVR
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| LL_ADC_IT_EOSMP
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| LL_ADC_IT_AWD1 )
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);
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/* Reset register ISR */
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SET_BIT(ADCx->ISR,
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( LL_ADC_FLAG_ADRDY
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| LL_ADC_FLAG_EOC
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| LL_ADC_FLAG_EOS
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| LL_ADC_FLAG_OVR
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| LL_ADC_FLAG_EOSMP
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| LL_ADC_FLAG_AWD1 )
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);
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/* Reset register CR */
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/* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */
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/* "read-set": no direct reset applicable. */
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/* No action on register CR */
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/* Reset register CFGR1 */
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CLEAR_BIT(ADCx->CFGR1,
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( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN
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| ADC_CFGR1_AUTOFF | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD
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| ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES
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| ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN )
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);
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/* Reset register CFGR2 */
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/* Note: Update of ADC clock mode is conditioned to ADC state disabled: */
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/* already done above. */
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CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE);
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/* Reset register SMPR */
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CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP);
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/* Reset register TR */
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MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT);
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/* Reset register CHSELR */
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#if defined(ADC_CCR_VBATEN)
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CLEAR_BIT(ADCx->CHSELR,
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( ADC_CHSELR_CHSEL18 | ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
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| ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
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| ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
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| ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
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| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
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);
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#else
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CLEAR_BIT(ADCx->CHSELR,
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( ADC_CHSELR_CHSEL17 | ADC_CHSELR_CHSEL16
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| ADC_CHSELR_CHSEL15 | ADC_CHSELR_CHSEL14 | ADC_CHSELR_CHSEL13 | ADC_CHSELR_CHSEL12
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| ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL10 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8
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| ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4
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| ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 )
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);
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#endif
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/* Reset register DR */
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/* bits in access mode read only, no direct reset applicable */
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}
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else
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{
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/* ADC instance is in an unknown state */
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/* Need to performing a hard reset of ADC instance, using high level */
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/* clock source RCC ADC reset. */
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/* Caution: On this STM32 serie, if several ADC instances are available */
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/* on the selected device, RCC ADC reset will reset */
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/* all ADC instances belonging to the common ADC instance. */
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status = ERROR;
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}
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return status;
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}
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/**
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* @brief Initialize some features of ADC instance.
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* @note These parameters have an impact on ADC scope: ADC instance.
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* Refer to corresponding unitary functions into
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* @ref ADC_LL_EF_Configuration_ADC_Instance .
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* @note The setting of these parameters by function @ref LL_ADC_Init()
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* is conditioned to ADC state:
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* ADC instance must be disabled.
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* This condition is applied to all ADC features, for efficiency
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* and compatibility over all STM32 families. However, the different
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* features can be set under different ADC state conditions
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* (setting possible with ADC enabled without conversion on going,
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* ADC enabled with conversion on going, ...)
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* Each feature can be updated afterwards with a unitary function
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* and potentially with ADC in a different state than disabled,
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* refer to description of each function for setting
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* conditioned to ADC state.
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* @note After using this function, some other features must be configured
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* using LL unitary functions.
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* The minimum configuration remaining to be done is:
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* - Set ADC group regular sequencer:
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* map channel on rank corresponding to channel number.
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* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
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* - Set ADC channel sampling time
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* Refer to function LL_ADC_SetChannelSamplingTime();
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* @param ADCx ADC instance
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* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: ADC registers are initialized
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* - ERROR: ADC registers are not initialized
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*/
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ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
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{
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ErrorStatus status = SUCCESS;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(ADCx));
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assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock));
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assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
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assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
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assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
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/* Note: Hardware constraint (refer to description of this function): */
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/* ADC instance must be disabled. */
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if(LL_ADC_IsEnabled(ADCx) == 0U)
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{
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/* Configuration of ADC hierarchical scope: */
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/* - ADC instance */
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/* - Set ADC data resolution */
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/* - Set ADC conversion data alignment */
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/* - Set ADC low power mode */
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MODIFY_REG(ADCx->CFGR1,
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ADC_CFGR1_RES
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| ADC_CFGR1_ALIGN
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| ADC_CFGR1_WAIT
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| ADC_CFGR1_AUTOFF
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,
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ADC_InitStruct->Resolution
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| ADC_InitStruct->DataAlignment
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| ADC_InitStruct->LowPowerMode
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);
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}
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else
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{
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/* Initialization error: ADC instance is not disabled. */
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status = ERROR;
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}
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return status;
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}
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/**
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* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
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* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
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* whose fields will be set to default values.
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* @retval None
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*/
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void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
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{
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/* Set ADC_InitStruct fields to default values */
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/* Set fields of ADC instance */
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ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
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ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
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ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
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ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
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}
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/**
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* @brief Initialize some features of ADC group regular.
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* @note These parameters have an impact on ADC scope: ADC group regular.
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* Refer to corresponding unitary functions into
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* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
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* (functions with prefix "REG").
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* @note The setting of these parameters by function @ref LL_ADC_Init()
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* is conditioned to ADC state:
|
|
* ADC instance must be disabled.
|
|
* This condition is applied to all ADC features, for efficiency
|
|
* and compatibility over all STM32 families. However, the different
|
|
* features can be set under different ADC state conditions
|
|
* (setting possible with ADC enabled without conversion on going,
|
|
* ADC enabled with conversion on going, ...)
|
|
* Each feature can be updated afterwards with a unitary function
|
|
* and potentially with ADC in a different state than disabled,
|
|
* refer to description of each function for setting
|
|
* conditioned to ADC state.
|
|
* @note After using this function, other features must be configured
|
|
* using LL unitary functions.
|
|
* The minimum configuration remaining to be done is:
|
|
* - Set ADC group regular sequencer:
|
|
* map channel on rank corresponding to channel number.
|
|
* Refer to function @ref LL_ADC_REG_SetSequencerChannels();
|
|
* - Set ADC channel sampling time
|
|
* Refer to function LL_ADC_SetChannelSamplingTime();
|
|
* @param ADCx ADC instance
|
|
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
|
* @retval An ErrorStatus enumeration value:
|
|
* - SUCCESS: ADC registers are initialized
|
|
* - ERROR: ADC registers are not initialized
|
|
*/
|
|
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
|
|
{
|
|
ErrorStatus status = SUCCESS;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
|
|
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
|
|
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
|
|
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
|
|
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
|
|
assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
|
|
|
|
/* Note: Hardware constraint (refer to description of this function): */
|
|
/* ADC instance must be disabled. */
|
|
if(LL_ADC_IsEnabled(ADCx) == 0U)
|
|
{
|
|
/* Configuration of ADC hierarchical scope: */
|
|
/* - ADC group regular */
|
|
/* - Set ADC group regular trigger source */
|
|
/* - Set ADC group regular sequencer discontinuous mode */
|
|
/* - Set ADC group regular continuous mode */
|
|
/* - Set ADC group regular conversion data transfer: no transfer or */
|
|
/* transfer by DMA, and DMA requests mode */
|
|
/* - Set ADC group regular overrun behavior */
|
|
/* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
|
|
/* setting of trigger source to SW start. */
|
|
MODIFY_REG(ADCx->CFGR1,
|
|
ADC_CFGR1_EXTSEL
|
|
| ADC_CFGR1_EXTEN
|
|
| ADC_CFGR1_DISCEN
|
|
| ADC_CFGR1_CONT
|
|
| ADC_CFGR1_DMAEN
|
|
| ADC_CFGR1_DMACFG
|
|
| ADC_CFGR1_OVRMOD
|
|
,
|
|
ADC_REG_InitStruct->TriggerSource
|
|
| ADC_REG_InitStruct->SequencerDiscont
|
|
| ADC_REG_InitStruct->ContinuousMode
|
|
| ADC_REG_InitStruct->DMATransfer
|
|
| ADC_REG_InitStruct->Overrun
|
|
);
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Initialization error: ADC instance is not disabled. */
|
|
status = ERROR;
|
|
}
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
|
|
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
|
|
* whose fields will be set to default values.
|
|
* @retval None
|
|
*/
|
|
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
|
|
{
|
|
/* Set ADC_REG_InitStruct fields to default values */
|
|
/* Set fields of ADC group regular */
|
|
/* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
|
|
/* setting of trigger source to SW start. */
|
|
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
|
|
ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
|
|
ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
|
|
ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
|
|
ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* ADC1 */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|