122 lines
3.1 KiB
C
122 lines
3.1 KiB
C
// Main starting point for SAM3/SAM4 boards
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//
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// Copyright (C) 2016-2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "board/armcm_boot.h" // armcm_main
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#include "board/irq.h" // irq_disable
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#include "board/usb_cdc.h" // usb_request_bootloader
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#include "command.h" // DECL_COMMAND_FLAGS
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#include "internal.h" // WDT
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#include "sched.h" // sched_main
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/****************************************************************
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* watchdog handler
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****************************************************************/
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void
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watchdog_reset(void)
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{
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WDT->WDT_CR = 0xA5000001;
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}
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DECL_TASK(watchdog_reset);
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void
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watchdog_init(void)
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{
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uint32_t timeout = 500 * 32768 / 128 / 1000; // 500ms timeout
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WDT->WDT_MR = WDT_MR_WDRSTEN | WDT_MR_WDV(timeout) | WDT_MR_WDD(timeout);
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}
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DECL_INIT(watchdog_init);
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/****************************************************************
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* Peripheral clocks
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****************************************************************/
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// Check if a peripheral clock has been enabled
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int
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is_enabled_pclock(uint32_t id)
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{
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if (id < 32)
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return !!(PMC->PMC_PCSR0 & (1 << id));
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else
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return !!(PMC->PMC_PCSR1 & (1 << (id - 32)));
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}
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// Enable a peripheral clock
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void
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enable_pclock(uint32_t id)
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{
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if (id < 32)
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PMC->PMC_PCER0 = 1 << id;
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else
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PMC->PMC_PCER1 = 1 << (id - 32);
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}
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/****************************************************************
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* Resets
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****************************************************************/
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void
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command_reset(uint32_t *args)
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{
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irq_disable();
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RSTC->RSTC_CR = ((0xA5 << RSTC_CR_KEY_Pos) | RSTC_CR_PROCRST
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| RSTC_CR_PERRST);
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for (;;)
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;
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}
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DECL_COMMAND_FLAGS(command_reset, HF_IN_SHUTDOWN, "reset");
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#if CONFIG_MACH_SAM3X || CONFIG_MACH_SAM4S
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#define EFC_HW EFC0
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#elif CONFIG_MACH_SAM4E
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#define EFC_HW EFC
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#endif
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void noinline __aligned(16) // align for predictable flash code access
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usb_request_bootloader(void)
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{
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irq_disable();
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// Request boot from ROM (instead of boot from flash)
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while ((EFC_HW->EEFC_FSR & EEFC_FSR_FRDY) == 0)
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;
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EFC_HW->EEFC_FCR = (EEFC_FCR_FCMD_CGPB | EEFC_FCR_FARG(1)
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| EEFC_FCR_FKEY_PASSWD);
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while ((EFC_HW->EEFC_FSR & EEFC_FSR_FRDY) == 0)
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;
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// Reboot
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RSTC->RSTC_CR = ((0xA5 << RSTC_CR_KEY_Pos) | RSTC_CR_PROCRST
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| RSTC_CR_PERRST);
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for (;;)
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;
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}
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/****************************************************************
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* Startup
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****************************************************************/
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static void
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matrix_init(void)
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{
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// The ATSAM sram is in a "no default master" state at reset
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// (despite the specs). That typically adds 1 wait cycle to every
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// memory access. Set it to "last access master" to avoid that.
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MATRIX->MATRIX_SCFG[0] = (MATRIX_SCFG_SLOT_CYCLE(64)
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| MATRIX_SCFG_DEFMSTR_TYPE(1));
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}
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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armcm_main(void)
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{
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SystemInit();
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matrix_init();
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sched_main();
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}
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