569 lines
18 KiB
C
569 lines
18 KiB
C
/**
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******************************************************************************
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* @file stm32f0xx_ll_pwr.h
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* @author MCD Application Team
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* @brief Header file of PWR LL module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F0xx_LL_PWR_H
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#define __STM32F0xx_LL_PWR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f0xx.h"
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/** @addtogroup STM32F0xx_LL_Driver
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* @{
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*/
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#if defined(PWR)
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/** @defgroup PWR_LL PWR
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
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* @{
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*/
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/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
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* @brief Flags defines which can be used with LL_PWR_WriteReg function
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* @{
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*/
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#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
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#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
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/**
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* @}
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*/
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/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
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* @brief Flags defines which can be used with LL_PWR_ReadReg function
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* @{
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*/
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#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
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#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
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#if defined(PWR_PVD_SUPPORT)
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#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
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#endif /* PWR_PVD_SUPPORT */
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#if defined(PWR_CSR_VREFINTRDYF)
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#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
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#endif /* PWR_CSR_VREFINTRDYF */
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#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
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#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
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#if defined(PWR_CSR_EWUP3)
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#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
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#endif /* PWR_CSR_EWUP3 */
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#if defined(PWR_CSR_EWUP4)
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#define LL_PWR_CSR_EWUP4 PWR_CSR_EWUP4 /*!< Enable WKUP pin 4 */
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#endif /* PWR_CSR_EWUP4 */
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#if defined(PWR_CSR_EWUP5)
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#define LL_PWR_CSR_EWUP5 PWR_CSR_EWUP5 /*!< Enable WKUP pin 5 */
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#endif /* PWR_CSR_EWUP5 */
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#if defined(PWR_CSR_EWUP6)
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#define LL_PWR_CSR_EWUP6 PWR_CSR_EWUP6 /*!< Enable WKUP pin 6 */
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#endif /* PWR_CSR_EWUP6 */
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#if defined(PWR_CSR_EWUP7)
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#define LL_PWR_CSR_EWUP7 PWR_CSR_EWUP7 /*!< Enable WKUP pin 7 */
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#endif /* PWR_CSR_EWUP7 */
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#if defined(PWR_CSR_EWUP8)
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#define LL_PWR_CSR_EWUP8 PWR_CSR_EWUP8 /*!< Enable WKUP pin 8 */
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#endif /* PWR_CSR_EWUP8 */
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/**
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* @}
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*/
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/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
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* @{
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*/
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#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
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#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
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#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
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/**
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* @}
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*/
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#if defined(PWR_CR_LPDS)
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/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
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* @{
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*/
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#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
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#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
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/**
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* @}
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*/
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#endif /* PWR_CR_LPDS */
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#if defined(PWR_PVD_SUPPORT)
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/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
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* @{
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*/
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#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold 0 */
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#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold 1 */
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#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold 2 */
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#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold 3 */
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#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold 4 */
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#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold 5 */
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#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold 6 */
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#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold 7 */
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/**
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* @}
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*/
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#endif /* PWR_PVD_SUPPORT */
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/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
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* @{
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*/
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#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
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#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
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#if defined(PWR_CSR_EWUP3)
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#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
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#endif /* PWR_CSR_EWUP3 */
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#if defined(PWR_CSR_EWUP4)
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#define LL_PWR_WAKEUP_PIN4 (PWR_CSR_EWUP4) /*!< WKUP pin 4 : LLG TBD */
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#endif /* PWR_CSR_EWUP4 */
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#if defined(PWR_CSR_EWUP5)
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#define LL_PWR_WAKEUP_PIN5 (PWR_CSR_EWUP5) /*!< WKUP pin 5 : LLG TBD */
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#endif /* PWR_CSR_EWUP5 */
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#if defined(PWR_CSR_EWUP6)
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#define LL_PWR_WAKEUP_PIN6 (PWR_CSR_EWUP6) /*!< WKUP pin 6 : LLG TBD */
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#endif /* PWR_CSR_EWUP6 */
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#if defined(PWR_CSR_EWUP7)
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#define LL_PWR_WAKEUP_PIN7 (PWR_CSR_EWUP7) /*!< WKUP pin 7 : LLG TBD */
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#endif /* PWR_CSR_EWUP7 */
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#if defined(PWR_CSR_EWUP8)
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#define LL_PWR_WAKEUP_PIN8 (PWR_CSR_EWUP8) /*!< WKUP pin 8 : LLG TBD */
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#endif /* PWR_CSR_EWUP8 */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
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* @{
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*/
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/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
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* @{
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*/
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/**
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* @brief Write a value in PWR register
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
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/**
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* @brief Read a value in PWR register
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
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* @{
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*/
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/** @defgroup PWR_LL_EF_Configuration Configuration
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* @{
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*/
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/**
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* @brief Enable access to the backup domain
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* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
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{
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SET_BIT(PWR->CR, PWR_CR_DBP);
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}
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/**
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* @brief Disable access to the backup domain
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* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_DBP);
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}
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/**
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* @brief Check if the backup domain is enabled
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* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
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}
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#if defined(PWR_CR_LPDS)
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/**
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* @brief Set voltage Regulator mode during deep sleep mode
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* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
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* @param RegulMode This parameter can be one of the following values:
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* @arg @ref LL_PWR_REGU_DSMODE_MAIN
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* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
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{
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MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
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}
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/**
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* @brief Get voltage Regulator mode during deep sleep mode
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* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_PWR_REGU_DSMODE_MAIN
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* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
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*/
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__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
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{
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return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
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}
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#endif /* PWR_CR_LPDS */
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/**
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* @brief Set Power Down mode when CPU enters deepsleep
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* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
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* @rmtoll CR LPDS LL_PWR_SetPowerMode
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* @param PDMode This parameter can be one of the following values:
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* @arg @ref LL_PWR_MODE_STOP_MAINREGU
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* @arg @ref LL_PWR_MODE_STOP_LPREGU
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* @arg @ref LL_PWR_MODE_STANDBY
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
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{
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MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
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}
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/**
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* @brief Get Power Down mode when CPU enters deepsleep
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* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
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* @rmtoll CR LPDS LL_PWR_GetPowerMode
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_PWR_MODE_STOP_MAINREGU
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* @arg @ref LL_PWR_MODE_STOP_LPREGU
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* @arg @ref LL_PWR_MODE_STANDBY
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*/
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__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
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{
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return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
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}
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#if defined(PWR_PVD_SUPPORT)
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/**
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* @brief Configure the voltage threshold detected by the Power Voltage Detector
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* @rmtoll CR PLS LL_PWR_SetPVDLevel
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* @param PVDLevel This parameter can be one of the following values:
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* @arg @ref LL_PWR_PVDLEVEL_0
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* @arg @ref LL_PWR_PVDLEVEL_1
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* @arg @ref LL_PWR_PVDLEVEL_2
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* @arg @ref LL_PWR_PVDLEVEL_3
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* @arg @ref LL_PWR_PVDLEVEL_4
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* @arg @ref LL_PWR_PVDLEVEL_5
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* @arg @ref LL_PWR_PVDLEVEL_6
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* @arg @ref LL_PWR_PVDLEVEL_7
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
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{
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MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
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}
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/**
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* @brief Get the voltage threshold detection
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* @rmtoll CR PLS LL_PWR_GetPVDLevel
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_PWR_PVDLEVEL_0
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* @arg @ref LL_PWR_PVDLEVEL_1
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* @arg @ref LL_PWR_PVDLEVEL_2
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* @arg @ref LL_PWR_PVDLEVEL_3
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* @arg @ref LL_PWR_PVDLEVEL_4
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* @arg @ref LL_PWR_PVDLEVEL_5
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* @arg @ref LL_PWR_PVDLEVEL_6
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* @arg @ref LL_PWR_PVDLEVEL_7
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*/
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__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
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{
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return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
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}
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/**
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* @brief Enable Power Voltage Detector
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* @rmtoll CR PVDE LL_PWR_EnablePVD
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnablePVD(void)
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{
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SET_BIT(PWR->CR, PWR_CR_PVDE);
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}
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/**
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* @brief Disable Power Voltage Detector
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* @rmtoll CR PVDE LL_PWR_DisablePVD
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_DisablePVD(void)
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{
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CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
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}
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/**
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* @brief Check if Power Voltage Detector is enabled
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* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
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{
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return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
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}
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#endif /* PWR_PVD_SUPPORT */
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/**
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* @brief Enable the WakeUp PINx functionality
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* @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
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* @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
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* @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin\n
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* @rmtoll CSR EWUP4 LL_PWR_EnableWakeUpPin\n
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* @rmtoll CSR EWUP5 LL_PWR_EnableWakeUpPin\n
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* @rmtoll CSR EWUP6 LL_PWR_EnableWakeUpPin\n
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* @rmtoll CSR EWUP7 LL_PWR_EnableWakeUpPin\n
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* @rmtoll CSR EWUP8 LL_PWR_EnableWakeUpPin
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* @param WakeUpPin This parameter can be one of the following values:
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* @arg @ref LL_PWR_WAKEUP_PIN1
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* @arg @ref LL_PWR_WAKEUP_PIN2
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* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN4 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN6 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN7 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN8 (*)
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*
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* (*) not available on all devices
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* @retval None
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*/
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__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
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{
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SET_BIT(PWR->CSR, WakeUpPin);
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}
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/**
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* @brief Disable the WakeUp PINx functionality
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* @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
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* @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
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* @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin\n
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* @rmtoll CSR EWUP4 LL_PWR_DisableWakeUpPin\n
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* @rmtoll CSR EWUP5 LL_PWR_DisableWakeUpPin\n
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* @rmtoll CSR EWUP6 LL_PWR_DisableWakeUpPin\n
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* @rmtoll CSR EWUP7 LL_PWR_DisableWakeUpPin\n
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* @rmtoll CSR EWUP8 LL_PWR_DisableWakeUpPin
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* @param WakeUpPin This parameter can be one of the following values:
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* @arg @ref LL_PWR_WAKEUP_PIN1
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* @arg @ref LL_PWR_WAKEUP_PIN2
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* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN4 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN6 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN7 (*)
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* @arg @ref LL_PWR_WAKEUP_PIN8 (*)
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*
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* (*) not available on all devices
|
|
* @retval None
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|
*/
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__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
|
|
{
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CLEAR_BIT(PWR->CSR, WakeUpPin);
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}
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|
|
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/**
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* @brief Check if the WakeUp PINx functionality is enabled
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* @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
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* @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
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* @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin\n
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* @rmtoll CSR EWUP4 LL_PWR_IsEnabledWakeUpPin\n
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* @rmtoll CSR EWUP5 LL_PWR_IsEnabledWakeUpPin\n
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* @rmtoll CSR EWUP6 LL_PWR_IsEnabledWakeUpPin\n
|
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* @rmtoll CSR EWUP7 LL_PWR_IsEnabledWakeUpPin\n
|
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* @rmtoll CSR EWUP8 LL_PWR_IsEnabledWakeUpPin
|
|
* @param WakeUpPin This parameter can be one of the following values:
|
|
* @arg @ref LL_PWR_WAKEUP_PIN1
|
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* @arg @ref LL_PWR_WAKEUP_PIN2
|
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* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
|
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* @arg @ref LL_PWR_WAKEUP_PIN4 (*)
|
|
* @arg @ref LL_PWR_WAKEUP_PIN5 (*)
|
|
* @arg @ref LL_PWR_WAKEUP_PIN6 (*)
|
|
* @arg @ref LL_PWR_WAKEUP_PIN7 (*)
|
|
* @arg @ref LL_PWR_WAKEUP_PIN8 (*)
|
|
*
|
|
* (*) not available on all devices
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
|
|
{
|
|
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
|
|
}
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Get Wake-up Flag
|
|
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
|
|
{
|
|
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
|
|
}
|
|
|
|
/**
|
|
* @brief Get Standby Flag
|
|
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
|
|
{
|
|
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
|
|
}
|
|
|
|
#if defined(PWR_PVD_SUPPORT)
|
|
/**
|
|
* @brief Indicate whether VDD voltage is below the selected PVD threshold
|
|
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
|
|
{
|
|
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
|
|
}
|
|
#endif /* PWR_PVD_SUPPORT */
|
|
|
|
#if defined(PWR_CSR_VREFINTRDYF)
|
|
/**
|
|
* @brief Get Internal Reference VrefInt Flag
|
|
* @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
|
|
{
|
|
return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
|
|
}
|
|
#endif /* PWR_CSR_VREFINTRDYF */
|
|
/**
|
|
* @brief Clear Standby Flag
|
|
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
|
|
{
|
|
SET_BIT(PWR->CR, PWR_CR_CSBF);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear Wake-up Flags
|
|
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
|
|
{
|
|
SET_BIT(PWR->CR, PWR_CR_CWUF);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if defined(USE_FULL_LL_DRIVER)
|
|
/** @defgroup PWR_LL_EF_Init De-initialization function
|
|
* @{
|
|
*/
|
|
ErrorStatus LL_PWR_DeInit(void);
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* defined(PWR) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __STM32F0xx_LL_PWR_H */
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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