1304 lines
48 KiB
C
1304 lines
48 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_hal_rcc.c
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief RCC HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Reset and Clock Control (RCC) peripheral:
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* + Initialization and de-initialization functions
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* + Peripheral Control functions
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*
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@verbatim
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==============================================================================
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##### RCC specific features #####
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==============================================================================
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[..]
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After reset the device is running from Internal High Speed oscillator
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(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
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and all peripherals are off except internal SRAM, Flash and JTAG.
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(+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
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all peripherals mapped on these buses are running at HSI speed.
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(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
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(+) All GPIOs are in input floating state, except the JTAG pins which
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are assigned to be used for debug purpose.
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[..] Once the device started from reset, the user application has to:
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(+) Configure the clock source to be used to drive the System clock
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(if the application needs higher frequency/performance)
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(+) Configure the System clock frequency and Flash settings
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(+) Configure the AHB and APB buses prescalers
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(+) Enable the clock for the peripheral(s) to be used
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(+) Configure the clock source(s) for peripherals whose clocks are not
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derived from the System clock (I2S, RTC, ADC, USB OTG FS)
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##### RCC Limitations #####
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==============================================================================
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[..]
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A delay between an RCC peripheral clock enable and the effective peripheral
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enabling should be taken into account in order to manage the peripheral read/write
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from/to registers.
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(+) This delay depends on the peripheral mapping.
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(++) AHB & APB peripherals, 1 dummy read is necessary
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[..]
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Workarounds:
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(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
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inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @defgroup RCC RCC
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* @brief RCC HAL module driver
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* @{
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*/
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#ifdef HAL_RCC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup RCC_Private_Constants RCC Private Constants
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* @{
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*/
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/** @defgroup RCC_Private_Macros RCC Private Macros
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* @{
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*/
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#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
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#define MCO1_GPIO_PORT GPIOA
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#define MCO1_PIN GPIO_PIN_8
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/**
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* @}
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*/
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/* Private variables ---------------------------------------------------------*/
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/** @defgroup RCC_Private_Variables RCC Private Variables
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* @{
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*/
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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static void RCC_Delay(uint32_t mdelay);
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup RCC_Exported_Functions RCC Exported Functions
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* @{
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*/
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/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and Configuration functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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This section provides functions allowing to configure the internal/external oscillators
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(HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
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and APB2).
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[..] Internal/external clock and PLL configuration
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(#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
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the PLL as System clock source.
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(#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
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clock source.
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(#) HSE (high-speed external), 4 to 24 MHz (STM32F100xx) or 4 to 16 MHz (STM32F101x/STM32F102x/STM32F103x) or 3 to 25 MHz (STM32F105x/STM32F107x) crystal oscillator used directly or
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through the PLL as System clock source. Can be used also as RTC clock source.
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(#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
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(#) PLL (clocked by HSI or HSE), featuring different output clocks:
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(++) The first output is used to generate the high speed system clock (up to 72 MHz for STM32F10xxx or up to 24 MHz for STM32F100xx)
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(++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
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(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
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and if a HSE clock failure occurs(HSE used directly or through PLL as System
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clock source), the System clocks automatically switched to HSI and an interrupt
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is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
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(Non-Maskable Interrupt) exception vector.
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(#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI,
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HSE or PLL clock (divided by 2) on PA8 pin + PLL2CLK, PLL3CLK/2, PLL3CLK and XTI for STM32F105x/STM32F107x
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[..] System, AHB and APB buses clocks configuration
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(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
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HSE and PLL.
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The AHB clock (HCLK) is derived from System clock through configurable
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prescaler and used to clock the CPU, memory and peripherals mapped
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on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
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from AHB clock through configurable prescalers and used to clock
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the peripherals mapped on these buses. You can use
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"@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
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-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
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(+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
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divided by 128.
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(+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
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to work correctly. This clock is derived of the main PLL through PLL Multiplier.
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(+@) I2S interface on STM32F105x/STM32F107x can be derived from PLL3CLK
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(+@) IWDG clock which is always the LSI clock.
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(#) For STM32F10xxx, the maximum frequency of the SYSCLK and HCLK/PCLK2 is 72 MHz, PCLK1 36 MHz.
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For STM32F100xx, the maximum frequency of the SYSCLK and HCLK/PCLK1/PCLK2 is 24 MHz.
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Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
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@endverbatim
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* @{
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*/
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/*
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Additional consideration on the SYSCLK based on Latency settings:
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+-----------------------------------------------+
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| Latency | SYSCLK clock frequency (MHz) |
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|---------------|-------------------------------|
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|0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
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|---------------|-------------------------------|
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|1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
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|---------------|-------------------------------|
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|2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
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+-----------------------------------------------+
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*/
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/**
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* @brief Resets the RCC clock configuration to the default reset state.
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* @note The default reset state of the clock configuration is given below:
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* - HSI ON and used as system clock source
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* - HSE and PLL OFF
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* - AHB, APB1 and APB2 prescaler set to 1.
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* - CSS and MCO1 OFF
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* - All interrupts disabled
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* @note This function does not modify the configuration of the
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* - Peripheral clocks
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* - LSI, LSE and RTC clocks
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* @retval None
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*/
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void HAL_RCC_DeInit(void)
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{
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/* Switch SYSCLK to HSI */
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CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
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/* Reset HSEON, CSSON, & PLLON bits */
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CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
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/* Reset HSEBYP bit */
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CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
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/* Reset CFGR register */
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CLEAR_REG(RCC->CFGR);
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/* Set HSITRIM bits to the reset value */
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MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (0x10U << RCC_CR_HSITRIM_Pos));
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#if defined(RCC_CFGR2_SUPPORT)
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/* Reset CFGR2 register */
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CLEAR_REG(RCC->CFGR2);
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#endif /* RCC_CFGR2_SUPPORT */
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/* Disable all interrupts */
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CLEAR_REG(RCC->CIR);
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/* Update the SystemCoreClock global variable */
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SystemCoreClock = HSI_VALUE;
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}
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/**
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* @brief Initializes the RCC Oscillators according to the specified parameters in the
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* RCC_OscInitTypeDef.
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* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
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* contains the configuration information for the RCC Oscillators.
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* @note The PLL is not disabled when used as system clock.
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* @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
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* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
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* supported by this macro. User should request a transition to LSE Off
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* first and then LSE On or LSE Bypass.
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* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
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* supported by this macro. User should request a transition to HSE Off
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* first and then HSE On or HSE Bypass.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
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{
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uint32_t tickstart = 0U;
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/* Check the parameters */
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assert_param(RCC_OscInitStruct != NULL);
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assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
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/*------------------------------- HSE Configuration ------------------------*/
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if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
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{
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/* Check the parameters */
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assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
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/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
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if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
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|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
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{
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if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
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{
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return HAL_ERROR;
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}
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}
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else
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{
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/* Set the new HSE configuration ---------------------------------------*/
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__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
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/* Check the HSE State */
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if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
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{
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till HSE is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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else
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{
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till HSE is disabled */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
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{
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if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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}
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}
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/*----------------------------- HSI Configuration --------------------------*/
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if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
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{
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/* Check the parameters */
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assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
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assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
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/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
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if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
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|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
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{
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/* When HSI is used as system clock it will not disabled */
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if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
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{
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return HAL_ERROR;
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}
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/* Otherwise, just the calibration is allowed */
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else
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{
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/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
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__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
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}
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}
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else
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{
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/* Check the HSI State */
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if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
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{
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/* Enable the Internal High Speed oscillator (HSI). */
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__HAL_RCC_HSI_ENABLE();
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till HSI is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
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__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
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}
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else
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{
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/* Disable the Internal High Speed oscillator (HSI). */
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__HAL_RCC_HSI_DISABLE();
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till HSI is disabled */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
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{
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if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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}
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}
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/*------------------------------ LSI Configuration -------------------------*/
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if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
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{
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/* Check the parameters */
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assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
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/* Check the LSI State */
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if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
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{
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/* Enable the Internal Low Speed oscillator (LSI). */
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__HAL_RCC_LSI_ENABLE();
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till LSI is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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/* To have a fully stabilized clock in the specified range, a software delay of 1ms
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should be added.*/
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RCC_Delay(1);
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}
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else
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{
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/* Disable the Internal Low Speed oscillator (LSI). */
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__HAL_RCC_LSI_DISABLE();
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till LSI is disabled */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
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{
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if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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}
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/*------------------------------ LSE Configuration -------------------------*/
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if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
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{
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FlagStatus pwrclkchanged = RESET;
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/* Check the parameters */
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assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
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/* Update LSE configuration in Backup Domain control register */
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/* Requires to enable write access to Backup Domain of necessary */
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if(__HAL_RCC_PWR_IS_CLK_DISABLED())
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{
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__HAL_RCC_PWR_CLK_ENABLE();
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pwrclkchanged = SET;
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}
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if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
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{
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/* Enable write access to Backup domain */
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SET_BIT(PWR->CR, PWR_CR_DBP);
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/* Wait for Backup domain Write protection disable */
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tickstart = HAL_GetTick();
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while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
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{
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if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
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}
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/* Set the new LSE configuration -----------------------------------------*/
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__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
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/* Check the LSE State */
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if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
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{
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/* Get Start Tick */
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tickstart = HAL_GetTick();
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/* Wait till LSE is ready */
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while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
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{
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if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
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{
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return HAL_TIMEOUT;
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}
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}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Require to disable power clock if necessary */
|
|
if(pwrclkchanged == SET)
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
}
|
|
}
|
|
|
|
#if defined(RCC_CR_PLL2ON)
|
|
/*-------------------------------- PLL2 Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
|
|
if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
|
|
{
|
|
/* This bit can not be cleared if the PLL2 clock is used indirectly as system
|
|
clock (i.e. it is used as PLL clock entry that is used as system clock). */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
|
|
(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
|
|
((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
else
|
|
{
|
|
if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
|
|
assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
|
|
|
|
/* Prediv2 can be written only when the PLLI2S is disabled. */
|
|
/* Return an error only if new value is different from the programmed value */
|
|
if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
|
|
(__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Disable the main PLL2. */
|
|
__HAL_RCC_PLL2_DISABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL2 is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Configure the HSE prediv2 factor --------------------------------*/
|
|
__HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
|
|
|
|
/* Configure the main PLL2 multiplication factors. */
|
|
__HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
|
|
|
|
/* Enable the main PLL2. */
|
|
__HAL_RCC_PLL2_ENABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL2 is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set PREDIV1 source to HSE */
|
|
CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
|
|
|
|
/* Disable the main PLL2. */
|
|
__HAL_RCC_PLL2_DISABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL2 is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#endif /* RCC_CR_PLL2ON */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
{
|
|
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
|
|
assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
|
|
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/* Configure the HSE prediv factor --------------------------------*/
|
|
/* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
|
|
if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
|
|
{
|
|
/* Check the parameter */
|
|
assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
|
|
|
|
/* Set PREDIV1 source */
|
|
SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */
|
|
|
|
/* Set PREDIV1 Value */
|
|
__HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
|
|
}
|
|
|
|
/* Configure the main PLL clock source and multiplication factors. */
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
RCC_OscInitStruct->PLL.PLLMUL);
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is ready */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Initializes the CPU, AHB and APB buses clocks according to the specified
|
|
* parameters in the RCC_ClkInitStruct.
|
|
* @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
|
|
* contains the configuration information for the RCC peripheral.
|
|
* @param FLatency FLASH Latency
|
|
* The value of this parameter depend on device used within the same series
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
|
|
*
|
|
* @note The HSI is used (enabled by hardware) as system clock source after
|
|
* start-up from Reset, wake-up from STOP and STANDBY mode, or in case
|
|
* of failure of the HSE used directly or indirectly as system clock
|
|
* (if the Clock Security System CSS is enabled).
|
|
*
|
|
* @note A switch from one clock source to another occurs only if the target
|
|
* clock source is ready (clock stable after start-up delay or PLL locked).
|
|
* If a clock source which is not yet ready is selected, the switch will
|
|
* occur when the clock source will be ready.
|
|
* You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
|
|
* currently used as system clock source.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
uint32_t tickstart = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(RCC_ClkInitStruct != NULL);
|
|
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
|
|
assert_param(IS_FLASH_LATENCY(FLatency));
|
|
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) of the device. */
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
/*-------------------------- HCLK Configuration --------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
{
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
/* PLL is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
|
|
|
|
/* Get Start Tick */
|
|
tickstart = HAL_GetTick();
|
|
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
{
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
{
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
|
|
{
|
|
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
{
|
|
return HAL_TIMEOUT;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Decreasing the number of wait states because of lower CPU frequency */
|
|
if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
{
|
|
return HAL_ERROR;
|
|
}
|
|
}
|
|
#endif /* FLASH_ACR_LATENCY */
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
HAL_InitTick (TICK_INT_PRIORITY);
|
|
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
|
|
* @brief RCC clocks control functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
|
##### Peripheral Control functions #####
|
|
===============================================================================
|
|
[..]
|
|
This subsection provides a set of functions allowing to control the RCC Clocks
|
|
frequencies.
|
|
|
|
@endverbatim
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Selects the clock source to output on MCO pin.
|
|
* @note MCO pin should be configured in alternate function mode.
|
|
* @param RCC_MCOx specifies the output direction for the clock source.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
|
|
* @param RCC_MCOSource specifies the clock source to output.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
|
|
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
|
|
@if STM32F105xC
|
|
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
|
|
@endif
|
|
@if STM32F107xC
|
|
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected as MCO source
|
|
* @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected as MCO source
|
|
@endif
|
|
* @param RCC_MCODiv specifies the MCO DIV.
|
|
* This parameter can be one of the following values:
|
|
* @arg @ref RCC_MCODIV_1 no division applied to MCO clock
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
|
|
{
|
|
GPIO_InitTypeDef gpio = {0U};
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_MCO(RCC_MCOx));
|
|
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
|
|
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
|
|
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(RCC_MCOx);
|
|
UNUSED(RCC_MCODiv);
|
|
|
|
/* Configure the MCO1 pin in alternate function mode */
|
|
gpio.Mode = GPIO_MODE_AF_PP;
|
|
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
|
|
gpio.Pull = GPIO_NOPULL;
|
|
gpio.Pin = MCO1_PIN;
|
|
|
|
/* MCO1 Clock Enable */
|
|
MCO1_CLK_ENABLE();
|
|
|
|
HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
|
|
|
|
/* Configure the MCO clock source */
|
|
__HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
|
|
}
|
|
|
|
/**
|
|
* @brief Enables the Clock Security System.
|
|
* @note If a failure is detected on the HSE oscillator clock, this oscillator
|
|
* is automatically disabled and an interrupt is generated to inform the
|
|
* software about the failure (Clock Security System Interrupt, CSSI),
|
|
* allowing the MCU to perform rescue operations. The CSSI is linked to
|
|
* the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_EnableCSS(void)
|
|
{
|
|
*(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
|
|
}
|
|
|
|
/**
|
|
* @brief Disables the Clock Security System.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_DisableCSS(void)
|
|
{
|
|
*(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the SYSCLK frequency
|
|
* @note The system frequency computed by this function is not the real
|
|
* frequency in the chip. It is calculated based on the predefined
|
|
* constant and the selected clock source:
|
|
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
|
|
* @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
|
|
* divided by PREDIV factor(**)
|
|
* @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
|
|
* divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
|
|
* @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
|
|
* 8 MHz) but the real value may vary depending on the variations
|
|
* in voltage and temperature.
|
|
* @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
|
|
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
|
* frequency of the crystal used. Otherwise, this function may
|
|
* have wrong result.
|
|
*
|
|
* @note The result of this function could be not correct when using fractional
|
|
* value for HSE crystal.
|
|
*
|
|
* @note This function can be used by the user application to compute the
|
|
* baud-rate for the communication peripherals or configure other parameters.
|
|
*
|
|
* @note Each time SYSCLK changes, this function must be called to update the
|
|
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
const uint8_t aPLLMULFactorTable[14] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 0, 0, 13};
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
#else
|
|
const uint8_t aPLLMULFactorTable[16] = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
const uint8_t aPredivFactorTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
|
#else
|
|
const uint8_t aPredivFactorTable[2] = {1, 2};
|
|
#endif /*RCC_CFGR2_PREDIV1*/
|
|
|
|
#endif
|
|
uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
|
|
uint32_t sysclockfreq = 0U;
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
uint32_t prediv2 = 0U, pll2mul = 0U;
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
|
|
tmpreg = RCC->CFGR;
|
|
|
|
/* Get SYSCLK source -------------------------------------------------------*/
|
|
switch (tmpreg & RCC_CFGR_SWS)
|
|
{
|
|
case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
|
|
{
|
|
sysclockfreq = HSE_VALUE;
|
|
break;
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
|
|
{
|
|
pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
|
|
if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
|
|
{
|
|
#if defined(RCC_CFGR2_PREDIV1)
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
|
|
#else
|
|
prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
|
|
#endif /*RCC_CFGR2_PREDIV1*/
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
|
|
if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
|
|
{
|
|
/* PLL2 selected as Prediv1 source */
|
|
/* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
|
|
prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> RCC_CFGR2_PREDIV2_Pos) + 1;
|
|
pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> RCC_CFGR2_PLL2MUL_Pos) + 2;
|
|
pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv) * pllmul);
|
|
}
|
|
else
|
|
{
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
|
|
}
|
|
|
|
/* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
|
|
/* In this case need to divide pllclk by 2 */
|
|
if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> RCC_CFGR_PLLMULL_Pos])
|
|
{
|
|
pllclk = pllclk / 2;
|
|
}
|
|
#else
|
|
/* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
|
|
pllclk = (uint32_t)((HSE_VALUE / prediv) * pllmul);
|
|
#endif /*RCC_CFGR2_PREDIV1SRC*/
|
|
}
|
|
else
|
|
{
|
|
/* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
|
|
pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
|
|
}
|
|
sysclockfreq = pllclk;
|
|
break;
|
|
}
|
|
case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
|
|
default: /* HSI used as system clock */
|
|
{
|
|
sysclockfreq = HSI_VALUE;
|
|
break;
|
|
}
|
|
}
|
|
return sysclockfreq;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the HCLK frequency
|
|
* @note Each time HCLK changes, this function must be called to update the
|
|
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
|
|
* and updated within this function
|
|
* @retval HCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
return SystemCoreClock;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the PCLK1 frequency
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the PCLK2 frequency
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the RCC_OscInitStruct according to the internal
|
|
* RCC configuration registers.
|
|
* @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
|
|
* will be configured.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(RCC_OscInitStruct != NULL);
|
|
|
|
/* Set all possible values for the Oscillator type parameter ---------------*/
|
|
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
|
|
| RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
|
|
|
|
#if defined(RCC_CFGR2_PREDIV1SRC)
|
|
/* Get the Prediv1 source --------------------------------------------------*/
|
|
RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
|
|
#endif /* RCC_CFGR2_PREDIV1SRC */
|
|
|
|
/* Get the HSE configuration -----------------------------------------------*/
|
|
if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
|
|
{
|
|
RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
|
|
}
|
|
else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
|
|
{
|
|
RCC_OscInitStruct->HSEState = RCC_HSE_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
|
|
}
|
|
RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
|
|
|
|
/* Get the HSI configuration -----------------------------------------------*/
|
|
if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
|
|
{
|
|
RCC_OscInitStruct->HSIState = RCC_HSI_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
|
|
}
|
|
|
|
RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
|
|
|
|
/* Get the LSE configuration -----------------------------------------------*/
|
|
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
|
|
}
|
|
else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
|
|
}
|
|
|
|
/* Get the LSI configuration -----------------------------------------------*/
|
|
if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
|
|
{
|
|
RCC_OscInitStruct->LSIState = RCC_LSI_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
|
|
}
|
|
|
|
|
|
/* Get the PLL configuration -----------------------------------------------*/
|
|
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
|
|
{
|
|
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
|
|
}
|
|
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
|
|
RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
|
|
#if defined(RCC_CR_PLL2ON)
|
|
/* Get the PLL2 configuration -----------------------------------------------*/
|
|
if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
|
|
{
|
|
RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
|
|
}
|
|
else
|
|
{
|
|
RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
|
|
}
|
|
RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
|
|
RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
|
|
#endif /* RCC_CR_PLL2ON */
|
|
}
|
|
|
|
/**
|
|
* @brief Get the RCC_ClkInitStruct according to the internal
|
|
* RCC configuration registers.
|
|
* @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
|
|
* contains the current clock configuration.
|
|
* @param pFLatency Pointer on the Flash Latency.
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(RCC_ClkInitStruct != NULL);
|
|
assert_param(pFLatency != NULL);
|
|
|
|
/* Set all possible values for the Clock type parameter --------------------*/
|
|
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
|
|
|
|
/* Get the SYSCLK configuration --------------------------------------------*/
|
|
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
|
|
|
|
/* Get the HCLK configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
|
|
|
|
/* Get the APB1 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
|
|
|
|
/* Get the APB2 configuration ----------------------------------------------*/
|
|
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
|
|
|
|
#if defined(FLASH_ACR_LATENCY)
|
|
/* Get the Flash Wait State (Latency) configuration ------------------------*/
|
|
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
|
|
#else
|
|
/* For VALUE lines devices, only LATENCY_0 can be set*/
|
|
*pFLatency = (uint32_t)FLASH_LATENCY_0;
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* @brief This function handles the RCC CSS interrupt request.
|
|
* @note This API should be called under the NMI_Handler().
|
|
* @retval None
|
|
*/
|
|
void HAL_RCC_NMI_IRQHandler(void)
|
|
{
|
|
/* Check RCC CSSF flag */
|
|
if(__HAL_RCC_GET_IT(RCC_IT_CSS))
|
|
{
|
|
/* RCC Clock Security System interrupt user callback */
|
|
HAL_RCC_CSSCallback();
|
|
|
|
/* Clear RCC CSS pending bit */
|
|
__HAL_RCC_CLEAR_IT(RCC_IT_CSS);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief This function provides delay (in milliseconds) based on CPU cycles method.
|
|
* @param mdelay: specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
static void RCC_Delay(uint32_t mdelay)
|
|
{
|
|
__IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
|
|
do
|
|
{
|
|
__NOP();
|
|
}
|
|
while (Delay --);
|
|
}
|
|
|
|
/**
|
|
* @brief RCC Clock Security System interrupt callback
|
|
* @retval none
|
|
*/
|
|
__weak void HAL_RCC_CSSCallback(void)
|
|
{
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_RCC_CSSCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* HAL_RCC_MODULE_ENABLED */
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|