124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file system_hc32f460.c
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**
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** A detailed description is available at
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** @link Hc32f460SystemGroup Hc32f460System description @endlink
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**
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** - 2018-10-15 CDT First version
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**
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******************************************************************************/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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/**
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*******************************************************************************
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** \addtogroup Hc32f460SystemGroup
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******************************************************************************/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('define')
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******************************************************************************/
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//@{
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/**
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******************************************************************************
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** System Clock Frequency (Core Clock) Variable according CMSIS
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******************************************************************************/
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uint32_t HRC_VALUE = HRC_16MHz_VALUE;
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uint32_t SystemCoreClock = MRC_VALUE;
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/**
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******************************************************************************
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** \brief Setup the microcontroller system. Initialize the System and update
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** the SystemCoreClock variable.
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**
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** \param None
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** \return None
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******************************************************************************/
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void SystemInit(void)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */
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#endif
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// SystemCoreClock = 168000000ul;
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SystemCoreClockUpdate();
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}
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void SystemCoreClockUpdate(void) // Update SystemCoreClock variable
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{
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uint8_t tmp = 0u;
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uint32_t plln = 19u, pllp = 1u, pllm = 0u, pllsource = 0u;
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/* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */
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/* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */
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/* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */
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if (1UL == (HRC_FREQ_MON() & 1UL))
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{
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HRC_VALUE = HRC_16MHz_VALUE;
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}
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else
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{
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HRC_VALUE = HRC_20MHz_VALUE;
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}
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tmp = M4_SYSREG->CMU_CKSWR_f.CKSW;
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switch (tmp)
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{
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case 0x00: /* use internal high speed RC */
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SystemCoreClock = HRC_VALUE;
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break;
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case 0x01: /* use internal middle speed RC */
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SystemCoreClock = MRC_VALUE;
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break;
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case 0x02: /* use internal low speed RC */
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SystemCoreClock = LRC_VALUE;
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break;
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case 0x03: /* use external high speed OSC */
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SystemCoreClock = XTAL_VALUE;
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break;
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case 0x04: /* use external low speed OSC */
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SystemCoreClock = XTAL32_VALUE;
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break;
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case 0x05: /* use MPLL */
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/* PLLCLK = ((pllsrc / pllm) * plln) / pllp */
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pllsource = M4_SYSREG->CMU_PLLCFGR_f.PLLSRC;
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plln = M4_SYSREG->CMU_PLLCFGR_f.MPLLN;
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pllp = M4_SYSREG->CMU_PLLCFGR_f.MPLLP;
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pllm = M4_SYSREG->CMU_PLLCFGR_f.MPLLM;
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/* use exteranl high speed OSC as PLL source */
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if (0ul == pllsource)
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{
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SystemCoreClock = (XTAL_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul);
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}
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/* use interanl high RC as PLL source */
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else if (1ul == pllsource)
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{
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SystemCoreClock = (HRC_VALUE) / (pllm + 1ul) * (plln + 1ul) / (pllp + 1ul);
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}
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else
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{
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/* Reserved */
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}
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break;
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}
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}
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//@} // UsartGroup
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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