96 lines
6.2 KiB
C
96 lines
6.2 KiB
C
/**
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* \file
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*
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* \brief Instance description for DMAC
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*
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* Copyright (c) 2018 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_DMAC_INSTANCE_
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#define _SAMD21_DMAC_INSTANCE_
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/* ========== Register definition for DMAC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_DMAC_CTRL (0x41004800) /**< \brief (DMAC) Control */
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#define REG_DMAC_CRCCTRL (0x41004802) /**< \brief (DMAC) CRC Control */
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#define REG_DMAC_CRCDATAIN (0x41004804) /**< \brief (DMAC) CRC Data Input */
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#define REG_DMAC_CRCCHKSUM (0x41004808) /**< \brief (DMAC) CRC Checksum */
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#define REG_DMAC_CRCSTATUS (0x4100480C) /**< \brief (DMAC) CRC Status */
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#define REG_DMAC_DBGCTRL (0x4100480D) /**< \brief (DMAC) Debug Control */
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#define REG_DMAC_QOSCTRL (0x4100480E) /**< \brief (DMAC) QOS Control */
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#define REG_DMAC_SWTRIGCTRL (0x41004810) /**< \brief (DMAC) Software Trigger Control */
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#define REG_DMAC_PRICTRL0 (0x41004814) /**< \brief (DMAC) Priority Control 0 */
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#define REG_DMAC_INTPEND (0x41004820) /**< \brief (DMAC) Interrupt Pending */
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#define REG_DMAC_INTSTATUS (0x41004824) /**< \brief (DMAC) Interrupt Status */
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#define REG_DMAC_BUSYCH (0x41004828) /**< \brief (DMAC) Busy Channels */
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#define REG_DMAC_PENDCH (0x4100482C) /**< \brief (DMAC) Pending Channels */
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#define REG_DMAC_ACTIVE (0x41004830) /**< \brief (DMAC) Active Channel and Levels */
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#define REG_DMAC_BASEADDR (0x41004834) /**< \brief (DMAC) Descriptor Memory Section Base Address */
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#define REG_DMAC_WRBADDR (0x41004838) /**< \brief (DMAC) Write-Back Memory Section Base Address */
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#define REG_DMAC_CHID (0x4100483F) /**< \brief (DMAC) Channel ID */
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#define REG_DMAC_CHCTRLA (0x41004840) /**< \brief (DMAC) Channel Control A */
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#define REG_DMAC_CHCTRLB (0x41004844) /**< \brief (DMAC) Channel Control B */
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#define REG_DMAC_CHINTENCLR (0x4100484C) /**< \brief (DMAC) Channel Interrupt Enable Clear */
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#define REG_DMAC_CHINTENSET (0x4100484D) /**< \brief (DMAC) Channel Interrupt Enable Set */
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#define REG_DMAC_CHINTFLAG (0x4100484E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
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#define REG_DMAC_CHSTATUS (0x4100484F) /**< \brief (DMAC) Channel Status */
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#else
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#define REG_DMAC_CTRL (*(RwReg16*)0x41004800UL) /**< \brief (DMAC) Control */
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#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802UL) /**< \brief (DMAC) CRC Control */
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#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804UL) /**< \brief (DMAC) CRC Data Input */
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#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808UL) /**< \brief (DMAC) CRC Checksum */
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#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CUL) /**< \brief (DMAC) CRC Status */
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#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DUL) /**< \brief (DMAC) Debug Control */
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#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EUL) /**< \brief (DMAC) QOS Control */
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#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810UL) /**< \brief (DMAC) Software Trigger Control */
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#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814UL) /**< \brief (DMAC) Priority Control 0 */
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#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820UL) /**< \brief (DMAC) Interrupt Pending */
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#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824UL) /**< \brief (DMAC) Interrupt Status */
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#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828UL) /**< \brief (DMAC) Busy Channels */
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#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CUL) /**< \brief (DMAC) Pending Channels */
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#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830UL) /**< \brief (DMAC) Active Channel and Levels */
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#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
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#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
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#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FUL) /**< \brief (DMAC) Channel ID */
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#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840UL) /**< \brief (DMAC) Channel Control A */
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#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844UL) /**< \brief (DMAC) Channel Control B */
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#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */
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#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */
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#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
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#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FUL) /**< \brief (DMAC) Channel Status */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for DMAC peripheral ========== */
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#define DMAC_CH_BITS 4 // Number of bits to select channel
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#define DMAC_CH_NUM 12 // Number of channels
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#define DMAC_CLK_AHB_ID 5 // AHB clock index
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#define DMAC_EVIN_NUM 4 // Number of input events
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#define DMAC_EVOUT_NUM 4 // Number of output events
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#define DMAC_LVL_BITS 2 // Number of bit to select level priority
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#define DMAC_LVL_NUM 4 // Enable priority level number
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#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
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#define DMAC_TRIG_NUM 45 // Number of peripheral triggers
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#endif /* _SAMD21_DMAC_INSTANCE_ */
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