304 lines
21 KiB
C
304 lines
21 KiB
C
/**
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* \file
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*
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* \brief Component description for OSC32KCTRL
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \asf_license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License"); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the Licence at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAME54_OSC32KCTRL_COMPONENT_
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#define _SAME54_OSC32KCTRL_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR OSC32KCTRL */
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/* ========================================================================== */
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/** \addtogroup SAME54_OSC32KCTRL 32kHz Oscillators Control */
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/*@{*/
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#define OSC32KCTRL_U2400
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#define REV_OSC32KCTRL 0x100
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/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
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uint32_t :1; /*!< bit: 1 Reserved */
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uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
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uint32_t :29; /*!< bit: 3..31 Reserved */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} OSC32KCTRL_INTENCLR_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define OSC32KCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSC32KCTRL_INTENCLR offset) Interrupt Enable Clear */
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#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENCLR reset_value) Interrupt Enable Clear */
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#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable */
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#define OSC32KCTRL_INTENCLR_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos)
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#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable */
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#define OSC32KCTRL_INTENCLR_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos)
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#define OSC32KCTRL_INTENCLR_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENCLR) MASK Register */
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/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */
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uint32_t :1; /*!< bit: 1 Reserved */
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uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */
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uint32_t :29; /*!< bit: 3..31 Reserved */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} OSC32KCTRL_INTENSET_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define OSC32KCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSC32KCTRL_INTENSET offset) Interrupt Enable Set */
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#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTENSET reset_value) Interrupt Enable Set */
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#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable */
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#define OSC32KCTRL_INTENSET_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos)
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#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable */
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#define OSC32KCTRL_INTENSET_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos)
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#define OSC32KCTRL_INTENSET_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTENSET) MASK Register */
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/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union { // __I to avoid read-modify-write on write-to-clear register
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struct {
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__I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
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__I uint32_t :1; /*!< bit: 1 Reserved */
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__I uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
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__I uint32_t :29; /*!< bit: 3..31 Reserved */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} OSC32KCTRL_INTFLAG_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define OSC32KCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSC32KCTRL_INTFLAG offset) Interrupt Flag Status and Clear */
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#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */
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#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Ready */
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#define OSC32KCTRL_INTFLAG_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos)
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#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector */
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#define OSC32KCTRL_INTFLAG_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos)
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#define OSC32KCTRL_INTFLAG_MASK _U_(0x00000005) /**< \brief (OSC32KCTRL_INTFLAG) MASK Register */
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/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */
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uint32_t :1; /*!< bit: 1 Reserved */
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uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */
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uint32_t XOSC32KSW:1; /*!< bit: 3 XOSC32K Clock switch */
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uint32_t :28; /*!< bit: 4..31 Reserved */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} OSC32KCTRL_STATUS_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define OSC32KCTRL_STATUS_OFFSET 0x0C /**< \brief (OSC32KCTRL_STATUS offset) Power and Clocks Status */
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#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_STATUS reset_value) Power and Clocks Status */
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#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos 0 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Ready */
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#define OSC32KCTRL_STATUS_XOSC32KRDY (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos)
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#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos 2 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector */
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#define OSC32KCTRL_STATUS_XOSC32KFAIL (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos)
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#define OSC32KCTRL_STATUS_XOSC32KSW_Pos 3 /**< \brief (OSC32KCTRL_STATUS) XOSC32K Clock switch */
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#define OSC32KCTRL_STATUS_XOSC32KSW (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos)
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#define OSC32KCTRL_STATUS_MASK _U_(0x0000000D) /**< \brief (OSC32KCTRL_STATUS) MASK Register */
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/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */
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uint8_t :5; /*!< bit: 3.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} OSC32KCTRL_RTCCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define OSC32KCTRL_RTCCTRL_OFFSET 0x10 /**< \brief (OSC32KCTRL_RTCCTRL offset) RTC Clock Selection */
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#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_RTCCTRL reset_value) RTC Clock Selection */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos 0 /**< \brief (OSC32KCTRL_RTCCTRL) RTC Clock Selection */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
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#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
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#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< \brief (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< \brief (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
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#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
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#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
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#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos)
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#define OSC32KCTRL_RTCCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_RTCCTRL) MASK Register */
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/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint16_t :1; /*!< bit: 0 Reserved */
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uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
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uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
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uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
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uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
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uint16_t :1; /*!< bit: 5 Reserved */
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uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
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uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
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uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
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uint16_t :1; /*!< bit: 11 Reserved */
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uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
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uint16_t CGM:2; /*!< bit: 13..14 Control Gain Mode */
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uint16_t :1; /*!< bit: 15 Reserved */
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} bit; /*!< Structure used for bit access */
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uint16_t reg; /*!< Type used for register access */
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} OSC32KCTRL_XOSC32K_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define OSC32KCTRL_XOSC32K_OFFSET 0x14 /**< \brief (OSC32KCTRL_XOSC32K offset) 32kHz External Crystal Oscillator (XOSC32K) Control */
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#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080) /**< \brief (OSC32KCTRL_XOSC32K reset_value) 32kHz External Crystal Oscillator (XOSC32K) Control */
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#define OSC32KCTRL_XOSC32K_ENABLE_Pos 1 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Enable */
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#define OSC32KCTRL_XOSC32K_ENABLE (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos)
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#define OSC32KCTRL_XOSC32K_XTALEN_Pos 2 /**< \brief (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable */
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#define OSC32KCTRL_XOSC32K_XTALEN (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos)
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#define OSC32KCTRL_XOSC32K_EN32K_Pos 3 /**< \brief (OSC32KCTRL_XOSC32K) 32kHz Output Enable */
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#define OSC32KCTRL_XOSC32K_EN32K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos)
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#define OSC32KCTRL_XOSC32K_EN1K_Pos 4 /**< \brief (OSC32KCTRL_XOSC32K) 1kHz Output Enable */
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#define OSC32KCTRL_XOSC32K_EN1K (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos)
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#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos 6 /**< \brief (OSC32KCTRL_XOSC32K) Run in Standby */
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#define OSC32KCTRL_XOSC32K_RUNSTDBY (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
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#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos 7 /**< \brief (OSC32KCTRL_XOSC32K) On Demand Control */
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#define OSC32KCTRL_XOSC32K_ONDEMAND (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
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#define OSC32KCTRL_XOSC32K_STARTUP_Pos 8 /**< \brief (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time */
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#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos)
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#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
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#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos 12 /**< \brief (OSC32KCTRL_XOSC32K) Write Lock */
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#define OSC32KCTRL_XOSC32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos)
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#define OSC32KCTRL_XOSC32K_CGM_Pos 13 /**< \brief (OSC32KCTRL_XOSC32K) Control Gain Mode */
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#define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos)
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#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
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#define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1) /**< \brief (OSC32KCTRL_XOSC32K) Standard mode */
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#define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2) /**< \brief (OSC32KCTRL_XOSC32K) High Speed mode */
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#define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
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#define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos)
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#define OSC32KCTRL_XOSC32K_MASK _U_(0x77DE) /**< \brief (OSC32KCTRL_XOSC32K) MASK Register */
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/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t CFDEN:1; /*!< bit: 0 Clock Failure Detector Enable */
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uint8_t SWBACK:1; /*!< bit: 1 Clock Switch Back */
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uint8_t CFDPRESC:1; /*!< bit: 2 Clock Failure Detector Prescaler */
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uint8_t :5; /*!< bit: 3.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} OSC32KCTRL_CFDCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define OSC32KCTRL_CFDCTRL_OFFSET 0x16 /**< \brief (OSC32KCTRL_CFDCTRL offset) Clock Failure Detector Control */
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#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_CFDCTRL reset_value) Clock Failure Detector Control */
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#define OSC32KCTRL_CFDCTRL_CFDEN_Pos 0 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable */
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#define OSC32KCTRL_CFDCTRL_CFDEN (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos)
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#define OSC32KCTRL_CFDCTRL_SWBACK_Pos 1 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Switch Back */
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#define OSC32KCTRL_CFDCTRL_SWBACK (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos)
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#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos 2 /**< \brief (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler */
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#define OSC32KCTRL_CFDCTRL_CFDPRESC (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos)
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#define OSC32KCTRL_CFDCTRL_MASK _U_(0x07) /**< \brief (OSC32KCTRL_CFDCTRL) MASK Register */
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/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} OSC32KCTRL_EVCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define OSC32KCTRL_EVCTRL_OFFSET 0x17 /**< \brief (OSC32KCTRL_EVCTRL offset) Event Control */
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#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSC32KCTRL_EVCTRL reset_value) Event Control */
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#define OSC32KCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable */
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#define OSC32KCTRL_EVCTRL_CFDEO (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos)
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#define OSC32KCTRL_EVCTRL_MASK _U_(0x01) /**< \brief (OSC32KCTRL_EVCTRL) MASK Register */
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/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t :1; /*!< bit: 0 Reserved */
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uint32_t EN32K:1; /*!< bit: 1 Enable Out 32k */
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uint32_t EN1K:1; /*!< bit: 2 Enable Out 1k */
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uint32_t :5; /*!< bit: 3.. 7 Reserved */
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uint32_t CALIB:6; /*!< bit: 8..13 Oscillator Calibration */
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uint32_t :1; /*!< bit: 14 Reserved */
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uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */
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uint32_t :16; /*!< bit: 16..31 Reserved */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} OSC32KCTRL_OSCULP32K_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define OSC32KCTRL_OSCULP32K_OFFSET 0x1C /**< \brief (OSC32KCTRL_OSCULP32K offset) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
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#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00000000) /**< \brief (OSC32KCTRL_OSCULP32K reset_value) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
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#define OSC32KCTRL_OSCULP32K_EN32K_Pos 1 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 32k */
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#define OSC32KCTRL_OSCULP32K_EN32K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos)
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#define OSC32KCTRL_OSCULP32K_EN1K_Pos 2 /**< \brief (OSC32KCTRL_OSCULP32K) Enable Out 1k */
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#define OSC32KCTRL_OSCULP32K_EN1K (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos)
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#define OSC32KCTRL_OSCULP32K_CALIB_Pos 8 /**< \brief (OSC32KCTRL_OSCULP32K) Oscillator Calibration */
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#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos)
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#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
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#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos 15 /**< \brief (OSC32KCTRL_OSCULP32K) Write Lock */
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#define OSC32KCTRL_OSCULP32K_WRTLOCK (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos)
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#define OSC32KCTRL_OSCULP32K_MASK _U_(0x0000BF06) /**< \brief (OSC32KCTRL_OSCULP32K) MASK Register */
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/** \brief OSC32KCTRL hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
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__IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
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__IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
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__I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
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__IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 8) RTC Clock Selection */
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RoReg8 Reserved1[0x3];
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__IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
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__IO OSC32KCTRL_CFDCTRL_Type CFDCTRL; /**< \brief Offset: 0x16 (R/W 8) Clock Failure Detector Control */
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__IO OSC32KCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x17 (R/W 8) Event Control */
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RoReg8 Reserved2[0x4];
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__IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
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} Osc32kctrl;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */
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