74 lines
3.6 KiB
C
74 lines
3.6 KiB
C
/**
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* \file
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*
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* \brief Instance description for UART0
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_UART0_INSTANCE_H_
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#define _SAME70_UART0_INSTANCE_H_
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/* ========== Register definition for UART0 peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_UART0_CR (0x400E0800) /**< (UART0) Control Register */
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#define REG_UART0_MR (0x400E0804) /**< (UART0) Mode Register */
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#define REG_UART0_IER (0x400E0808) /**< (UART0) Interrupt Enable Register */
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#define REG_UART0_IDR (0x400E080C) /**< (UART0) Interrupt Disable Register */
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#define REG_UART0_IMR (0x400E0810) /**< (UART0) Interrupt Mask Register */
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#define REG_UART0_SR (0x400E0814) /**< (UART0) Status Register */
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#define REG_UART0_RHR (0x400E0818) /**< (UART0) Receive Holding Register */
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#define REG_UART0_THR (0x400E081C) /**< (UART0) Transmit Holding Register */
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#define REG_UART0_BRGR (0x400E0820) /**< (UART0) Baud Rate Generator Register */
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#define REG_UART0_CMPR (0x400E0824) /**< (UART0) Comparison Register */
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#define REG_UART0_WPMR (0x400E08E4) /**< (UART0) Write Protection Mode Register */
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#else
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#define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< (UART0) Control Register */
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#define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< (UART0) Mode Register */
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#define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< (UART0) Interrupt Enable Register */
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#define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< (UART0) Interrupt Disable Register */
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#define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< (UART0) Interrupt Mask Register */
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#define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< (UART0) Status Register */
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#define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< (UART0) Receive Holding Register */
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#define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< (UART0) Transmit Holding Register */
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#define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< (UART0) Baud Rate Generator Register */
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#define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< (UART0) Comparison Register */
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#define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< (UART0) Write Protection Mode Register */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for UART0 peripheral ========== */
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#define UART0_DMAC_ID_RX 21
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#define UART0_DMAC_ID_TX 20
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#define UART0_INSTANCE_ID 7
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#define UART0_CLOCK_ID 7
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#define UART0_BRSRCCK_PERIPH_CLK 0 /* MCK */
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#define UART0_BRSRCCK_PMC_PCK 0 /* PCK4 */
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#endif /* _SAME70_UART0_INSTANCE_ */
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