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#ifndef _SAM4E_UART1_INSTANCE_
#define _SAM4E_UART1_INSTANCE_

/* ========== Register definition for UART1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UART1_CR            (0x40060600U) /**< \brief (UART1) Control Register */
#define REG_UART1_MR            (0x40060604U) /**< \brief (UART1) Mode Register */
#define REG_UART1_IER           (0x40060608U) /**< \brief (UART1) Interrupt Enable Register */
#define REG_UART1_IDR           (0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */
#define REG_UART1_IMR           (0x40060610U) /**< \brief (UART1) Interrupt Mask Register */
#define REG_UART1_SR            (0x40060614U) /**< \brief (UART1) Status Register */
#define REG_UART1_RHR           (0x40060618U) /**< \brief (UART1) Receive Holding Register */
#define REG_UART1_THR           (0x4006061CU) /**< \brief (UART1) Transmit Holding Register */
#define REG_UART1_BRGR          (0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */
#define REG_UART1_RPR           (0x40060700U) /**< \brief (UART1) Receive Pointer Register */
#define REG_UART1_RCR           (0x40060704U) /**< \brief (UART1) Receive Counter Register */
#define REG_UART1_TPR           (0x40060708U) /**< \brief (UART1) Transmit Pointer Register */
#define REG_UART1_TCR           (0x4006070CU) /**< \brief (UART1) Transmit Counter Register */
#define REG_UART1_RNPR          (0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */
#define REG_UART1_RNCR          (0x40060714U) /**< \brief (UART1) Receive Next Counter Register */
#define REG_UART1_TNPR          (0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */
#define REG_UART1_TNCR          (0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */
#define REG_UART1_PTCR          (0x40060720U) /**< \brief (UART1) Transfer Control Register */
#define REG_UART1_PTSR          (0x40060724U) /**< \brief (UART1) Transfer Status Register */
#else
#define REG_UART1_CR   (*(WoReg*)0x40060600U) /**< \brief (UART1) Control Register */
#define REG_UART1_MR   (*(RwReg*)0x40060604U) /**< \brief (UART1) Mode Register */
#define REG_UART1_IER  (*(WoReg*)0x40060608U) /**< \brief (UART1) Interrupt Enable Register */
#define REG_UART1_IDR  (*(WoReg*)0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */
#define REG_UART1_IMR  (*(RoReg*)0x40060610U) /**< \brief (UART1) Interrupt Mask Register */
#define REG_UART1_SR   (*(RoReg*)0x40060614U) /**< \brief (UART1) Status Register */
#define REG_UART1_RHR  (*(RoReg*)0x40060618U) /**< \brief (UART1) Receive Holding Register */
#define REG_UART1_THR  (*(WoReg*)0x4006061CU) /**< \brief (UART1) Transmit Holding Register */
#define REG_UART1_BRGR (*(RwReg*)0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */
#define REG_UART1_RPR  (*(RwReg*)0x40060700U) /**< \brief (UART1) Receive Pointer Register */
#define REG_UART1_RCR  (*(RwReg*)0x40060704U) /**< \brief (UART1) Receive Counter Register */
#define REG_UART1_TPR  (*(RwReg*)0x40060708U) /**< \brief (UART1) Transmit Pointer Register */
#define REG_UART1_TCR  (*(RwReg*)0x4006070CU) /**< \brief (UART1) Transmit Counter Register */
#define REG_UART1_RNPR (*(RwReg*)0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */
#define REG_UART1_RNCR (*(RwReg*)0x40060714U) /**< \brief (UART1) Receive Next Counter Register */
#define REG_UART1_TNPR (*(RwReg*)0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */
#define REG_UART1_TNCR (*(RwReg*)0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */
#define REG_UART1_PTCR (*(WoReg*)0x40060720U) /**< \brief (UART1) Transfer Control Register */
#define REG_UART1_PTSR (*(RoReg*)0x40060724U) /**< \brief (UART1) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

#endif /* _SAM4E_UART1_INSTANCE_ */