Most samd boards have the crystal and it does improve the clock
accuracy, so default to enabling it.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Add support for using the internal clocks (with USB clock recovery
mode if available) on the SAMD21. Don't use the internal clock if the
external crystal is requested (instead use the PLL synced to the
external 32Khz signal).
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Add support for USB clock recovery mode if an external 32Khz crystal
is not in use. If using an external crystal, then don't use the
internal 48Mhz DFLL48Mhz clock (just use the PLLs synced to the
external 32Khz signal).
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
The SAMD51 ADC is only clocked on rising edges (vs both rising and
falling edges on the SAMD21) and it has a greater minimum frequency
than the SAMD21. So, increase the ADC clock.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
The cpu is almost always 16Mhz and the serial port is almost always
UART0, so no need to prompt in the normal case.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Now that the internal DWT timer is used for software timers, there is
no need to clock the peripherals at a higher clock speed. Clock all
peripherals at 48Mhz and simplify the clock generation code.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Clearing the watchdog while it is in progress can cause bus stalls on
the SAMD21. It appears that clearing the watchdog on the SAMD51 can
cause lockups of the watchdog device.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
The sram matrix configuration is, bizarrely, configured with a slow
default. It will typically add an extra wait state to every memory
access. Set the matrix sram controller to improve the performance.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Avoid using the "low-level" library timing utilities. This is in
preparation for using SysTick as part of the timer implementation.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
The ARM CortexM3 (and later) chips almost always have a 32bit timer in
the "Debug and Watch Trace" (DWT) unit which resides within the cpu
core itself. This timer is generally faster to access than timers
located on the chip's peripheral bus. When combined with the standard
ARM SysTick timer it provides a (generally) portable mechanism to
implement Klipper's software timer mechanism. It's generally also
faster than using the vendor specific timers.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Move the definition of SERIAL_BAUD to the main src/Kconfig file. Only
show this as an option if the user selects the ability to configure
low-level options.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
The lpc176x ADC is extremely noisy. Implement a 5 order median filter
on each ADC read to weed out obviously incorrect readings.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Order the adc config code so that a shutdown from gpio_adc_setup()
doesn't result in analog_in_shutdown() running on a 'struct analog_in'
that hasn't yet been configured.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Make sure to explicitly cast to 32bit integers when doing math on
16bit integers that require the extra precision as the AVR uses a
16bit int.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
The sam3 i2c code and the linux code use a 7-bit i2c address, while
the avr, lpc176x, and samd21 i2c code uses an 8-bit address with the
least significant bit always zero. A similar issue occurred in the
host code (sx1509.py and replicape.py use 7-bit addresses while
uc1701.py and mcp4451.py use 8-bit addresses).
Consistently use 7-bit addresses in all the code. This breaks
compatibility between host and mcu software, so make a change to the
config_i2c command to force users to synchronize software updates.
This also breaks common Smoothieboard configs, so update the mcp4451
code to validate the i2c_address.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Kevin O'Connor