lpc176x: Use common cmsis-core files
No need to include separate cmsis files from the mbed project - the standard CMSIS_5 files work fine. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
742048a08d
commit
f4910e119a
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@ -21,10 +21,10 @@ compile with gcc's LTO feature. See sam3x.patch for the modifications.
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The lpc176x directory contains code from the mbed project:
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The lpc176x directory contains code from the mbed project:
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https://github.com/ARMmbed/mbed-os
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https://github.com/ARMmbed/mbed-os
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version mbed-os-5.8.3 (c05d72c3c005fbb7e92c3994c32bda45218ae7fe).
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version mbed-os-5.8.3 (c05d72c3c005fbb7e92c3994c32bda45218ae7fe).
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Contents taken from the targets/TARGET_NXP/TARGET_LPC176X/ directory
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Contents taken from the targets/TARGET_NXP/TARGET_LPC176X/ directory.
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and the cmsis/TARGET_CORTEX_M/ directory. It has been modified to
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It has been modified to compile with gcc's LTO feature and to use
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compile with gcc's LTO feature and to use appropriate clock speeds on
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appropriate clock speeds on the LPC1768 and LPC1769. See lpc176x.patch
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the LPC1768 and LPC1769. See lpc176x.patch for the modifications.
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for the modifications.
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The cmsis-stm32f1 and the hal-stm32f1 directories contain code from
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The cmsis-stm32f1 and the hal-stm32f1 directories contain code from
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STMicroelectronics:
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STMicroelectronics:
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@ -1,257 +0,0 @@
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/**************************************************************************//**
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* @file cmsis_compiler.h
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* @brief CMSIS compiler generic header file
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* @version V5.0.2
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* @date 13. February 2017
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******************************************************************************/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __CMSIS_COMPILER_H
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#define __CMSIS_COMPILER_H
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#include <stdint.h>
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/*
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* ARM Compiler 4/5
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*/
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#if defined ( __CC_ARM )
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#include "cmsis_armcc.h"
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/*
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* ARM Compiler 6 (armclang)
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*/
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#include "cmsis_armclang.h"
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/*
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* GNU Compiler
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*/
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#elif defined ( __GNUC__ )
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#include "cmsis_gcc.h"
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/*
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* IAR Compiler
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*/
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#elif defined ( __ICCARM__ )
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#include <cmsis_iccarm.h>
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/*
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* TI ARM Compiler
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*/
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#elif defined ( __TI_ARM__ )
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#include <cmsis_ccs.h>
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static inline
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __attribute__((noreturn))
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#endif
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#ifndef __USED
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT struct __attribute__((packed))
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#endif
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#ifndef __PACKED_UNION
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#define __PACKED_UNION union __attribute__((packed))
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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struct __attribute__((packed)) T_UINT32 { uint32_t v; };
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#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#endif
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#ifndef __RESTRICT
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#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
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#define __RESTRICT
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#endif
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/*
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* TASKING Compiler
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*/
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#elif defined ( __TASKING__ )
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/*
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* The CMSIS functions have been implemented as intrinsics in the compiler.
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* Please use "carm -?i" to get an up to date list of all intrinsics,
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* Including the CMSIS ones.
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*/
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static inline
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __attribute__((noreturn))
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#endif
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#ifndef __USED
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __PACKED
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#define __PACKED __packed__
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT struct __packed__
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#endif
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#ifndef __PACKED_UNION
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#define __PACKED_UNION union __packed__
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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struct __packed__ T_UINT32 { uint32_t v; };
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#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#define __ALIGNED(x) __align(x)
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#endif
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#ifndef __RESTRICT
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#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
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#define __RESTRICT
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#endif
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/*
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* COSMIC Compiler
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*/
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#elif defined ( __CSMC__ )
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#include <cmsis_csm.h>
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#ifndef __ASM
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#define __ASM _asm
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#endif
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#ifndef __INLINE
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#define __INLINE inline
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static inline
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#endif
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#ifndef __NO_RETURN
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// NO RETURN is automatically detected hence no warning here
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#define __NO_RETURN
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#endif
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#ifndef __USED
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#warning No compiler specific solution for __USED. __USED is ignored.
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#define __USED
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#endif
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#ifndef __WEAK
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#define __WEAK __weak
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#endif
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#ifndef __PACKED
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#define __PACKED @packed
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT @packed struct
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#endif
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#ifndef __PACKED_UNION
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#define __PACKED_UNION @packed union
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#endif
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#ifndef __UNALIGNED_UINT32 /* deprecated */
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@packed struct T_UINT32 { uint32_t v; };
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#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
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#define __ALIGNED(x)
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#endif
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#ifndef __RESTRICT
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#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
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#define __RESTRICT
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#endif
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#else
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#error Unknown compiler.
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#endif
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#endif /* __CMSIS_COMPILER_H */
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File diff suppressed because it is too large
Load Diff
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@ -1,39 +0,0 @@
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/**************************************************************************//**
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* @file cmsis_version.h
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* @brief CMSIS Core(M) Version definitions
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* @version V5.0.2
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* @date 19. April 2017
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******************************************************************************/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#if defined ( __ICCARM__ )
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#pragma system_include /* treat file as system include file for MISRA check */
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#pragma clang system_header /* treat file as system include file */
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#endif
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#ifndef __CMSIS_VERSION_H
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#define __CMSIS_VERSION_H
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/* CMSIS Version definitions */
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#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
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#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(M) sub version */
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#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
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__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -1,191 +0,0 @@
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/******************************************************************************
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* @file mpu_armv7.h
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* @brief CMSIS MPU API for ARMv7 MPU
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* @version V5.0.3
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* @date 09. August 2017
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******************************************************************************/
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/*
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* Copyright (c) 2017 ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef ARM_MPU_ARMV7_H
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#define ARM_MPU_ARMV7_H
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#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
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#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
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#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
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#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
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#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
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#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
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#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
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#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
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#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
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#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
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#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
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#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
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#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
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#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
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#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
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|
||||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
|
|
||||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
|
|
||||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
|
|
||||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
|
|
||||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
|
|
||||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
|
|
||||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
|
|
||||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
|
|
||||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
|
|
||||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
|
|
||||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
|
|
||||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
|
|
||||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
|
|
||||||
|
|
||||||
#define ARM_MPU_AP_NONE 0U
|
|
||||||
#define ARM_MPU_AP_PRIV 1U
|
|
||||||
#define ARM_MPU_AP_URO 2U
|
|
||||||
#define ARM_MPU_AP_FULL 3U
|
|
||||||
#define ARM_MPU_AP_PRO 5U
|
|
||||||
#define ARM_MPU_AP_RO 6U
|
|
||||||
|
|
||||||
/** MPU Region Base Address Register Value
|
|
||||||
*
|
|
||||||
* \param Region The region to be configured, number 0 to 15.
|
|
||||||
* \param BaseAddress The base address for the region.
|
|
||||||
*/
|
|
||||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
|
||||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
|
||||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
|
||||||
(MPU_RBAR_VALID_Msk))
|
|
||||||
|
|
||||||
/**
|
|
||||||
* MPU Region Attribut and Size Register Value
|
|
||||||
*
|
|
||||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
|
||||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
|
||||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
|
||||||
* \param IsShareable Region is shareable between multiple bus masters.
|
|
||||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
|
||||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
|
||||||
* \param SubRegionDisable Sub-region disable field.
|
|
||||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
|
||||||
*/
|
|
||||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
|
||||||
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
|
||||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
|
||||||
(((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
|
||||||
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
|
||||||
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
|
||||||
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
|
|
||||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
|
||||||
(((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
|
||||||
(MPU_RASR_ENABLE_Msk))
|
|
||||||
|
|
||||||
|
|
||||||
/**
|
|
||||||
* Struct for a single MPU Region
|
|
||||||
*/
|
|
||||||
typedef struct _ARM_MPU_Region_t {
|
|
||||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
|
||||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
|
||||||
} ARM_MPU_Region_t;
|
|
||||||
|
|
||||||
/** Enable the MPU.
|
|
||||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
|
||||||
{
|
|
||||||
__DSB();
|
|
||||||
__ISB();
|
|
||||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
|
||||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
|
||||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Disable the MPU.
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
|
||||||
{
|
|
||||||
__DSB();
|
|
||||||
__ISB();
|
|
||||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
|
||||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
|
||||||
#endif
|
|
||||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Clear and disable the given MPU region.
|
|
||||||
* \param rnr Region number to be cleared.
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
|
||||||
{
|
|
||||||
MPU->RNR = rnr;
|
|
||||||
MPU->RASR = 0U;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Configure an MPU region.
|
|
||||||
* \param rbar Value for RBAR register.
|
|
||||||
* \param rsar Value for RSAR register.
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
|
||||||
{
|
|
||||||
MPU->RBAR = rbar;
|
|
||||||
MPU->RASR = rasr;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Configure the given MPU region.
|
|
||||||
* \param rnr Region number to be configured.
|
|
||||||
* \param rbar Value for RBAR register.
|
|
||||||
* \param rsar Value for RSAR register.
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
|
||||||
{
|
|
||||||
MPU->RNR = rnr;
|
|
||||||
MPU->RBAR = rbar;
|
|
||||||
MPU->RASR = rasr;
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
|
||||||
* \param dst Destination data is copied to.
|
|
||||||
* \param src Source data is copied from.
|
|
||||||
* \param len Amount of data words to be copied.
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
|
||||||
{
|
|
||||||
uint32_t i;
|
|
||||||
for (i = 0U; i < len; ++i)
|
|
||||||
{
|
|
||||||
dst[i] = src[i];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/** Load the given number of MPU regions from a table.
|
|
||||||
* \param table Pointer to the MPU configuration table.
|
|
||||||
* \param cnt Amount of regions to be configured.
|
|
||||||
*/
|
|
||||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
|
||||||
{
|
|
||||||
static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
|
||||||
if (cnt > MPU_TYPE_RALIASES) {
|
|
||||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
|
||||||
ARM_MPU_Load(table+MPU_TYPE_RALIASES, cnt-MPU_TYPE_RALIASES);
|
|
||||||
} else {
|
|
||||||
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -4,10 +4,10 @@
|
||||||
CROSS_PREFIX=arm-none-eabi-
|
CROSS_PREFIX=arm-none-eabi-
|
||||||
|
|
||||||
dirs-y += src/lpc176x src/generic
|
dirs-y += src/lpc176x src/generic
|
||||||
dirs-y += lib/lpc176x/device lib/lpc176x/device/TOOLCHAIN_GCC_ARM
|
dirs-y += lib/lpc176x/device/TOOLCHAIN_GCC_ARM
|
||||||
|
|
||||||
CFLAGS += -mthumb -mcpu=cortex-m3
|
CFLAGS += -mthumb -mcpu=cortex-m3
|
||||||
CFLAGS += -Ilib/lpc176x/device -Ilib/lpc176x/device -Ilib/lpc176x/cmsis
|
CFLAGS += -Ilib/lpc176x/device -Ilib/cmsis-core
|
||||||
|
|
||||||
CFLAGS_klipper.elf += -T $(OUT)LPC1768.ld
|
CFLAGS_klipper.elf += -T $(OUT)LPC1768.ld
|
||||||
CFLAGS_klipper.elf += --specs=nano.specs --specs=nosys.specs
|
CFLAGS_klipper.elf += --specs=nano.specs --specs=nosys.specs
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue