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stm32f4: Add support for external 8Mhz crystal 

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2019-07-25 23:50:12 -04:00
parent 658088b753
commit f3d7287a28
2 changed files with 23 additions and 5 deletions
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8
src/stm32f4/Kconfig
View File

@ -15,6 +15,14 @@ config CLOCK_FREQ
int int
default 180000000 default 180000000
choice
prompt "Clock Reference"
config STM32F4_CLOCK_REF_8M
bool "8Mhz crystal"
config STM32F4_CLOCK_REF_INTERNAL
bool "Internal clock"
endchoice
config SERIAL config SERIAL
bool bool
default y default y

16
src/stm32f4/clock.c
View File

@ -4,6 +4,7 @@
// //
// This file may be distributed under the terms of the GNU GPLv3 license. // This file may be distributed under the terms of the GNU GPLv3 license.
#include "autoconf.h" // CONFIG_STM32F4_CLOCK_REF_8M
#include "internal.h" // enable_pclock #include "internal.h" // enable_pclock
#define FREQ_PERIPH 45000000 #define FREQ_PERIPH 45000000
@ -38,11 +39,20 @@ get_pclock_frequency(uint32_t periph_base)
void void
clock_setup(void) clock_setup(void)
{ {
// Configure 180Mhz PLL from internal oscillator (HSI) if (CONFIG_STM32F4_CLOCK_REF_8M) {
// Configure 180Mhz PLL from external 8Mhz crystal (HSE)
RCC->CR |= RCC_CR_HSEON;
RCC->PLLCFGR = ( RCC->PLLCFGR = (
RCC_PLLCFGR_PLLSRC_HSI | (16 << RCC_PLLCFGR_PLLM_Pos) RCC_PLLCFGR_PLLSRC_HSE | (4 << RCC_PLLCFGR_PLLM_Pos)
| (360 << RCC_PLLCFGR_PLLN_Pos) | (0 << RCC_PLLCFGR_PLLP_Pos) | (180 << RCC_PLLCFGR_PLLN_Pos) | (0 << RCC_PLLCFGR_PLLP_Pos)
| (7 << RCC_PLLCFGR_PLLQ_Pos) | (6 << RCC_PLLCFGR_PLLR_Pos)); | (7 << RCC_PLLCFGR_PLLQ_Pos) | (6 << RCC_PLLCFGR_PLLR_Pos));
} else {
// Configure 180Mhz PLL from internal 16Mhz oscillator (HSI)
RCC->PLLCFGR = (
RCC_PLLCFGR_PLLSRC_HSI | (8 << RCC_PLLCFGR_PLLM_Pos)
| (180 << RCC_PLLCFGR_PLLN_Pos) | (0 << RCC_PLLCFGR_PLLP_Pos)
| (7 << RCC_PLLCFGR_PLLQ_Pos) | (6 << RCC_PLLCFGR_PLLR_Pos));
}
RCC->CR |= RCC_CR_PLLON; RCC->CR |= RCC_CR_PLLON;
// Enable "over drive" // Enable "over drive"