stm32: Minor changes to stm32g0b0 ifdefs
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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@ -88,7 +88,7 @@
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#if CONFIG_MACH_STM32G0
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// Some of the stm32g0 MCUs have slightly different register names
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#ifdef LPUART2
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#if CONFIG_MACH_STM32G0B1
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#define USART2_IRQn USART2_LPUART2_IRQn
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#endif
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#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
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@ -28,9 +28,11 @@
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#define TIMx TIM3
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#define TIMx_IRQn TIM3_IRQn
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#define HAVE_TIMER_32BIT 0
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#ifdef TIM4
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#define TIM3_IRQn TIM3_TIM4_IRQn
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#endif
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// Some chips have slightly different register names
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#if CONFIG_MACH_STM32G0B0
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#define TIM3_IRQn TIM3_TIM4_IRQn
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#endif
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static inline uint32_t
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@ -60,8 +60,8 @@ lookup_clock_line(uint32_t periph_base)
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return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<18};
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if (periph_base == ADC1_BASE)
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return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<20};
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if (periph_base >= APBPERIPH_BASE && periph_base < APBPERIPH_BASE + 0x8000)
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{
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if (periph_base >= APBPERIPH_BASE
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&& periph_base < APBPERIPH_BASE + 32*0x400) {
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uint32_t bit = 1 << ((periph_base - APBPERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APBENR1, .rst=&RCC->APBRSTR1, .bit=bit};
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}
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