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stm32: Minor changes to stm32g0b0 ifdefs 

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2022-12-15 10:23:37 -05:00
parent e33b41abaa
commit f31540b357
3 changed files with 8 additions and 6 deletions
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2
src/stm32/stm32f0_serial.c
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@ -88,7 +88,7 @@
#if CONFIG_MACH_STM32G0 #if CONFIG_MACH_STM32G0
// Some of the stm32g0 MCUs have slightly different register names // Some of the stm32g0 MCUs have slightly different register names
#ifdef LPUART2 #if CONFIG_MACH_STM32G0B1
#define USART2_IRQn USART2_LPUART2_IRQn #define USART2_IRQn USART2_LPUART2_IRQn
#endif #endif
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE

8
src/stm32/stm32f0_timer.c
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@ -28,9 +28,11 @@
#define TIMx TIM3 #define TIMx TIM3
#define TIMx_IRQn TIM3_IRQn #define TIMx_IRQn TIM3_IRQn
#define HAVE_TIMER_32BIT 0 #define HAVE_TIMER_32BIT 0
#ifdef TIM4 #endif
#define TIM3_IRQn TIM3_TIM4_IRQn
#endif // Some chips have slightly different register names
#if CONFIG_MACH_STM32G0B0
#define TIM3_IRQn TIM3_TIM4_IRQn
#endif #endif
static inline uint32_t static inline uint32_t

4
src/stm32/stm32g0.c
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@ -60,8 +60,8 @@ lookup_clock_line(uint32_t periph_base)
return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<18}; return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<18};
if (periph_base == ADC1_BASE) if (periph_base == ADC1_BASE)
return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<20}; return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<20};
if (periph_base >= APBPERIPH_BASE && periph_base < APBPERIPH_BASE + 0x8000) if (periph_base >= APBPERIPH_BASE
{ && periph_base < APBPERIPH_BASE + 32*0x400) {
uint32_t bit = 1 << ((periph_base - APBPERIPH_BASE) / 0x400); uint32_t bit = 1 << ((periph_base - APBPERIPH_BASE) / 0x400);
return (struct cline){.en=&RCC->APBENR1, .rst=&RCC->APBRSTR1, .bit=bit}; return (struct cline){.en=&RCC->APBENR1, .rst=&RCC->APBRSTR1, .bit=bit};
} }