diff --git a/src/stm32/stm32f0_serial.c b/src/stm32/stm32f0_serial.c
index 4e0f39fe..4f6495f7 100644
--- a/src/stm32/stm32f0_serial.c
+++ b/src/stm32/stm32f0_serial.c
@@ -88,7 +88,7 @@
 
 #if CONFIG_MACH_STM32G0
   // Some of the stm32g0 MCUs have slightly different register names
-  #ifdef LPUART2
+  #if CONFIG_MACH_STM32G0B1
     #define USART2_IRQn USART2_LPUART2_IRQn
   #endif
   #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
diff --git a/src/stm32/stm32f0_timer.c b/src/stm32/stm32f0_timer.c
index 0d8ed3a3..f4a96396 100644
--- a/src/stm32/stm32f0_timer.c
+++ b/src/stm32/stm32f0_timer.c
@@ -28,9 +28,11 @@
   #define TIMx TIM3
   #define TIMx_IRQn TIM3_IRQn
   #define HAVE_TIMER_32BIT 0
-  #ifdef TIM4
-    #define TIM3_IRQn TIM3_TIM4_IRQn
-  #endif
+#endif
+
+// Some chips have slightly different register names
+#if CONFIG_MACH_STM32G0B0
+  #define TIM3_IRQn TIM3_TIM4_IRQn
 #endif
 
 static inline uint32_t
diff --git a/src/stm32/stm32g0.c b/src/stm32/stm32g0.c
index 84711709..f42ac777 100644
--- a/src/stm32/stm32g0.c
+++ b/src/stm32/stm32g0.c
@@ -60,8 +60,8 @@ lookup_clock_line(uint32_t periph_base)
         return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<18};
     if (periph_base == ADC1_BASE)
         return (struct cline){.en=&RCC->APBENR2,.rst=&RCC->APBRSTR2,.bit=1<<20};
-    if (periph_base >= APBPERIPH_BASE && periph_base < APBPERIPH_BASE + 0x8000)
-    {
+    if (periph_base >= APBPERIPH_BASE
+        && periph_base < APBPERIPH_BASE + 32*0x400) {
         uint32_t bit = 1 << ((periph_base - APBPERIPH_BASE) / 0x400);
         return (struct cline){.en=&RCC->APBENR1, .rst=&RCC->APBRSTR1, .bit=bit};
     }