From f2179da8adfaff9862f12982713b27150c9bd9d1 Mon Sep 17 00:00:00 2001 From: Kevin O'Connor Date: Fri, 30 Nov 2018 20:00:01 -0500 Subject: [PATCH] samd21: Add support for hardware pwm Signed-off-by: Kevin O'Connor --- src/samd21/Kconfig | 1 + src/samd21/Makefile | 1 + src/samd21/gpio.h | 6 +++ src/samd21/hard_pwm.c | 102 ++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 110 insertions(+) create mode 100644 src/samd21/hard_pwm.c diff --git a/src/samd21/Kconfig b/src/samd21/Kconfig index 858fcca5..225eae17 100644 --- a/src/samd21/Kconfig +++ b/src/samd21/Kconfig @@ -8,6 +8,7 @@ config SAMD_SELECT select HAVE_GPIO select HAVE_GPIO_I2C select HAVE_GPIO_SPI + select HAVE_GPIO_HARD_PWM select HAVE_GPIO_BITBANGING config BOARD_DIRECTORY diff --git a/src/samd21/Makefile b/src/samd21/Makefile index a5135d24..34de8e48 100644 --- a/src/samd21/Makefile +++ b/src/samd21/Makefile @@ -22,6 +22,7 @@ src-$(CONFIG_USBSERIAL) += samd21/usbserial.c generic/usb_cdc.c src-$(CONFIG_SERIAL) += samd21/serial.c generic/serial_irq.c src-$(CONFIG_HAVE_GPIO_I2C) += samd21/i2c.c src-$(CONFIG_HAVE_GPIO_SPI) += samd21/spi.c +src-$(CONFIG_HAVE_GPIO_HARD_PWM) += samd21/hard_pwm.c # Support bootloader offset address target-y := $(OUT)samd21.ld $(target-y) diff --git a/src/samd21/gpio.h b/src/samd21/gpio.h index 41787b85..6c910da8 100644 --- a/src/samd21/gpio.h +++ b/src/samd21/gpio.h @@ -21,6 +21,12 @@ struct gpio_in gpio_in_setup(uint8_t pin, int8_t pull_up); void gpio_in_reset(struct gpio_in g, int8_t pull_up); uint8_t gpio_in_read(struct gpio_in g); +struct gpio_pwm { + void *reg; +}; +struct gpio_pwm gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val); +void gpio_pwm_write(struct gpio_pwm g, uint8_t val); + struct spi_config { uint32_t ctrla, baud; }; diff --git a/src/samd21/hard_pwm.c b/src/samd21/hard_pwm.c new file mode 100644 index 00000000..7deecfb9 --- /dev/null +++ b/src/samd21/hard_pwm.c @@ -0,0 +1,102 @@ +// Hardware PWM support on samd21 +// +// Copyright (C) 2018 Kevin O'Connor +// +// This file may be distributed under the terms of the GNU GPLv3 license. + +#include "command.h" // shutdown +#include "gpio.h" // gpio_pwm_write +#include "internal.h" // GPIO +#include "samd21.h" // TCC0 +#include "sched.h" // sched_shutdown + +struct gpio_pwm_info { + uint32_t gpio; + Tcc *tcc; + uint32_t clock_id, power_id, channel; + char ptype; +}; + +static const struct gpio_pwm_info pwm_regs[] = { + { GPIO('A', 4), TCC0, TCC0_GCLK_ID, PM_APBCMASK_TCC0, 0, 'E' }, + { GPIO('A', 5), TCC0, TCC0_GCLK_ID, PM_APBCMASK_TCC0, 1, 'E' }, + { GPIO('A', 6), TCC1, TCC1_GCLK_ID, PM_APBCMASK_TCC1, 0, 'E' }, + { GPIO('A', 7), TCC1, TCC1_GCLK_ID, PM_APBCMASK_TCC1, 1, 'E' }, + { GPIO('A', 8), TCC0, TCC0_GCLK_ID, PM_APBCMASK_TCC0, 0, 'E' }, + { GPIO('A', 9), TCC0, TCC0_GCLK_ID, PM_APBCMASK_TCC0, 1, 'E' }, + { GPIO('A', 10), TCC1, TCC1_GCLK_ID, PM_APBCMASK_TCC1, 0, 'E' }, + { GPIO('A', 11), TCC1, TCC1_GCLK_ID, PM_APBCMASK_TCC1, 1, 'E' }, + { GPIO('A', 12), TCC2, TCC2_GCLK_ID, PM_APBCMASK_TCC2, 0, 'E' }, + { GPIO('A', 13), TCC2, TCC2_GCLK_ID, PM_APBCMASK_TCC2, 1, 'E' }, + { GPIO('A', 16), TCC2, TCC2_GCLK_ID, PM_APBCMASK_TCC2, 0, 'E' }, + { GPIO('A', 17), TCC2, TCC2_GCLK_ID, PM_APBCMASK_TCC2, 1, 'E' }, + { GPIO('A', 18), TCC0, TCC0_GCLK_ID, PM_APBCMASK_TCC0, 2, 'F' }, + { GPIO('A', 19), TCC0, TCC0_GCLK_ID, PM_APBCMASK_TCC0, 3, 'F' }, + { GPIO('A', 24), TCC1, TCC1_GCLK_ID, PM_APBCMASK_TCC1, 2, 'F' }, + { GPIO('A', 25), TCC1, TCC1_GCLK_ID, PM_APBCMASK_TCC1, 3, 'F' }, + { GPIO('A', 30), TCC1, TCC1_GCLK_ID, PM_APBCMASK_TCC1, 0, 'E' }, + { GPIO('A', 31), TCC1, TCC1_GCLK_ID, PM_APBCMASK_TCC1, 1, 'E' }, + { GPIO('B', 30), TCC0, TCC0_GCLK_ID, PM_APBCMASK_TCC0, 0, 'E' }, + { GPIO('B', 31), TCC0, TCC0_GCLK_ID, PM_APBCMASK_TCC0, 1, 'E' }, +}; + +#define MAX_PWM 255 + +DECL_CONSTANT(PWM_MAX, MAX_PWM); + +struct gpio_pwm +gpio_pwm_setup(uint8_t pin, uint32_t cycle_time, uint8_t val) +{ + // Find pin in pwm_regs table + const struct gpio_pwm_info *p = pwm_regs; + for (; ; p++) { + if (p >= &pwm_regs[ARRAY_SIZE(pwm_regs)]) + shutdown("Not a valid PWM pin"); + if (p->gpio == pin) + break; + } + + // Enable timer clock + enable_pclock(p->clock_id, p->power_id); + + // Map cycle_time to pwm clock divisor + uint32_t cs; + switch (cycle_time) { + case 0 ... (1+2) * MAX_PWM / 2 - 1: cs = 0; break; + case (1+2) * MAX_PWM / 2 ... (2+4) * MAX_PWM / 2 - 1: cs = 1; break; + case (2+4) * MAX_PWM / 2 ... (4+8) * MAX_PWM / 2 - 1: cs = 2; break; + case (4+8) * MAX_PWM / 2 ... (8+16) * MAX_PWM / 2 - 1: cs = 3; break; + case (8+16) * MAX_PWM / 2 ... (16+64) * MAX_PWM / 2 - 1: cs = 4; break; + case (16+64) * MAX_PWM / 2 ... (64+256) * MAX_PWM / 2 - 1: cs = 5; break; + case (64+256) * MAX_PWM / 2 ... (256+1024) * MAX_PWM / 2 - 1: cs = 6; break; + default: cs = 7; break; + } + uint32_t ctrla = TCC_CTRLA_ENABLE | TCC_CTRLA_PRESCALER(cs); + + // Enable timer + Tcc *tcc = p->tcc; + uint32_t old_ctrla = tcc->CTRLA.reg; + if (old_ctrla != ctrla) { + if (old_ctrla & TCC_CTRLA_ENABLE) + shutdown("PWM already programmed at different speed"); + tcc->CTRLA.reg = ctrla & ~TCC_CTRLA_ENABLE; + tcc->WAVE.reg = TCC_WAVE_WAVEGEN_NPWM; + tcc->PER.reg = MAX_PWM; + tcc->CTRLA.reg = ctrla; + } + + // Set initial value + struct gpio_pwm g = (struct gpio_pwm) { (void*)&tcc->CCB[p->channel].reg }; + gpio_pwm_write(g, val); + + // Route output to pin + gpio_peripheral(pin, p->ptype, 0); + + return g; +} + +void +gpio_pwm_write(struct gpio_pwm g, uint8_t val) +{ + *(volatile uint32_t*)g.reg = val; +}