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stm32: Simplify CFGR register setup in stm32h7_adc.c 

On all chips, the JQDIS bit is set and the CONT, RES, ALIGN bits are
clear after a reset.  There is no need to program the OVRMOD bit.  Use
the same logic across chips to help unify the adc implementation.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2022-12-13 10:44:35 -05:00
parent 9b7dcfa333
commit efdc29f589
1 changed files with 2 additions and 10 deletions
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12
src/stm32/stm32h7_adc.c
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@ -296,15 +296,9 @@ gpio_adc_setup(uint32_t pin)
| (aticks << 9) | (aticks << 12) | (aticks << 15) | (aticks << 9) | (aticks << 12) | (aticks << 15)
| (aticks << 18) | (aticks << 21) | (aticks << 24) | (aticks << 18) | (aticks << 21) | (aticks << 24)
| (aticks << 27)); | (aticks << 27));
// Disable Continuous Mode
MODIFY_REG(adc->CFGR, ADC_CFGR_CONT_Msk, 0);
// Set to 12 bit // Set to 12 bit
if (is_stm32h723_adc3) { if (!is_stm32h723_adc3) {
#ifdef ADC3_CFGR_RES
MODIFY_REG(adc->CFGR, ADC3_CFGR_RES_Msk, 0 << ADC3_CFGR_RES_Pos);
MODIFY_REG(adc->CFGR, ADC3_CFGR_ALIGN_Msk, 0<<ADC3_CFGR_ALIGN_Pos);
#endif
} else {
MODIFY_REG(adc->CFGR, ADC_CFGR_RES_Msk, ADC_RES<<ADC_CFGR_RES_Pos); MODIFY_REG(adc->CFGR, ADC_CFGR_RES_Msk, ADC_RES<<ADC_CFGR_RES_Pos);
} }
#if CONFIG_MACH_STM32H7 #if CONFIG_MACH_STM32H7
@ -321,8 +315,6 @@ gpio_adc_setup(uint32_t pin)
} }
MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSS_Msk, MODIFY_REG(adc->CFGR2, ADC_CFGR2_OVSS_Msk,
OVERSAMPLES_EXPONENT << ADC_CFGR2_OVSS_Pos); OVERSAMPLES_EXPONENT << ADC_CFGR2_OVSS_Pos);
#else // stm32l4
adc->CFGR |= ADC_CFGR_JQDIS | ADC_CFGR_OVRMOD;
#endif #endif
} }