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stm32: No need for fdcan_ram global pointer in fdcan.c 

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2022-10-04 11:28:25 -04:00
parent 465aaf383f
commit ef98cd9aba
1 changed files with 10 additions and 24 deletions
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34
src/stm32/fdcan.c
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@ -46,10 +46,10 @@
#if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3) #if !(CONFIG_STM32_CANBUS_PB0_PB1 || CONFIG_STM32_CANBUS_PC2_PC3)
#define SOC_CAN FDCAN1 #define SOC_CAN FDCAN1
#define MSG_RAM fdcan_ram->fdcan1 #define MSG_RAM (((FDCAN_RAM_TypeDef*)SRAMCAN_BASE)->fdcan1)
#else #else
#define SOC_CAN FDCAN2 #define SOC_CAN FDCAN2
#define MSG_RAM fdcan_ram->fdcan2 #define MSG_RAM (((FDCAN_RAM_TypeDef*)SRAMCAN_BASE)->fdcan2)
#endif #endif
#if CONFIG_MACH_STM32G0 #if CONFIG_MACH_STM32G0
@ -88,8 +88,6 @@ typedef struct {
FDCAN_MSG_RAM_TypeDef fdcan2; FDCAN_MSG_RAM_TypeDef fdcan2;
} FDCAN_RAM_TypeDef; } FDCAN_RAM_TypeDef;
FDCAN_RAM_TypeDef *fdcan_ram = (FDCAN_RAM_TypeDef *)(SRAMCAN_BASE);
/**************************************************************** /****************************************************************
* CANbus code * CANbus code
@ -154,7 +152,8 @@ canbus_set_filter(uint32_t id)
SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos SOC_CAN->RXGFC = ((id ? 3 : 1) << FDCAN_RXGFC_LSS_Pos
| 0x02 << FDCAN_RXGFC_ANFS_Pos); | 0x02 << FDCAN_RXGFC_ANFS_Pos);
#elif CONFIG_MACH_STM32H7 #elif CONFIG_MACH_STM32H7
SOC_CAN->SIDFC |= (id ? 3 : 1) << FDCAN_SIDFC_LSS_Pos; uint32_t flssa = (uint32_t)MSG_RAM.FLS - SRAMCAN_BASE;
SOC_CAN->SIDFC = flssa | ((id ? 3 : 1) << FDCAN_SIDFC_LSS_Pos);
SOC_CAN->GFC = 0x02 << FDCAN_GFC_ANFS_Pos; SOC_CAN->GFC = 0x02 << FDCAN_GFC_ANFS_Pos;
#endif #endif
@ -279,25 +278,12 @@ can_init(void)
SOC_CAN->NBTP = btr; SOC_CAN->NBTP = btr;
#if CONFIG_MACH_STM32H7 #if CONFIG_MACH_STM32H7
/* /* Setup message RAM addresses */
The Message RAM of STM32H7 is settable uint32_t f0sa = (uint32_t)MSG_RAM.RXF0 - SRAMCAN_BASE;
So we set it to be consistent with STM32G0 SOC_CAN->RXF0C = f0sa | (ARRAY_SIZE(MSG_RAM.RXF0) << FDCAN_RXF0C_F0S_Pos);
*/ SOC_CAN->RXESC = (7 << FDCAN_RXESC_F1DS_Pos) | (7 << FDCAN_RXESC_F0DS_Pos);
uint32_t flssa = (uint32_t)&MSG_RAM - (uint32_t)&fdcan_ram->fdcan1; uint32_t tbsa = (uint32_t)MSG_RAM.TXFIFO - SRAMCAN_BASE;
uint32_t f0sa = flssa + SOC_CAN->TXBC = tbsa | (ARRAY_SIZE(MSG_RAM.TXFIFO) << FDCAN_TXBC_TFQS_Pos);
(((uint32_t)MSG_RAM.RXF0 - (uint32_t)MSG_RAM.FLS) / 4);
uint32_t tbsa = f0sa +
(((uint32_t)MSG_RAM.TXFIFO - (uint32_t)MSG_RAM.RXF0) / 4);
SOC_CAN->SIDFC = flssa << FDCAN_SIDFC_FLSSA_Pos;
SOC_CAN->RXF0C = ((f0sa << FDCAN_RXF0C_F0SA_Pos)
| (3 << FDCAN_RXF0C_F0S_Pos));
SOC_CAN->RXESC = ((7 << FDCAN_RXESC_F1DS_Pos)
| (7 << FDCAN_RXESC_F0DS_Pos));
SOC_CAN->TXBC = ((tbsa << FDCAN_TXBC_TBSA_Pos)
| (3 << FDCAN_TXBC_TFQS_Pos));
SOC_CAN->TXESC = 7 << FDCAN_TXESC_TBDS_Pos; SOC_CAN->TXESC = 7 << FDCAN_TXESC_TBDS_Pos;
#endif #endif