diff --git a/src/stm32f4/adc.c b/src/stm32f4/adc.c
index e112c2a0..00eac8f0 100644
--- a/src/stm32f4/adc.c
+++ b/src/stm32f4/adc.c
@@ -44,7 +44,7 @@ gpio_adc_setup(uint32_t pin)
                    | (aticks << 21) | (aticks << 24) | (aticks << 27));
     ADC1->CR2 = ADC_CR2_ADON;
 
-    gpio_peripheral(pin, GPIO_ANALOG, 0, 0);
+    gpio_peripheral(pin, GPIO_ANALOG, 0);
 
     return (struct gpio_adc){ .chan = chan };
 }
diff --git a/src/stm32f4/gpio.c b/src/stm32f4/gpio.c
index ce5b275b..707eaf18 100644
--- a/src/stm32f4/gpio.c
+++ b/src/stm32f4/gpio.c
@@ -21,16 +21,17 @@ static GPIO_TypeDef * const digital_regs[] = {
 
 // Set the mode and extended function of a pin
 void
-gpio_peripheral(uint32_t gpio, uint32_t mode, uint32_t func, int pullup)
+gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
 {
     GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
+    uint32_t mode_bits = mode & 0x0f, func = mode >> 4;
     uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
     uint32_t pos = gpio % 16, af_reg = pos / 8;
     uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
     uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
 
     regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
-    regs->MODER = (regs->MODER & ~m_msk) | (mode << m_shift);
+    regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
     regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
     regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift);
 }
@@ -74,7 +75,7 @@ gpio_out_reset(struct gpio_out g, uint32_t val)
         regs->BSRR = g.bit;
     else
         regs->BSRR = g.bit << 16;
-    gpio_peripheral(pin, GPIO_OUTPUT, 0, 0);
+    gpio_peripheral(pin, GPIO_OUTPUT, 0);
     irq_restore(flag);
 }
 
@@ -123,7 +124,7 @@ gpio_in_reset(struct gpio_in g, int32_t pull_up)
     GPIO_TypeDef *regs = g.regs;
     int pin = regs_to_pin(regs, g.bit);
     irqstatus_t flag = irq_save();
-    gpio_peripheral(pin, GPIO_INPUT, 0, pull_up);
+    gpio_peripheral(pin, GPIO_INPUT, pull_up);
     irq_restore(flag);
 }
 
diff --git a/src/stm32f4/internal.h b/src/stm32f4/internal.h
index 0cfb2664..f1c2fd66 100644
--- a/src/stm32f4/internal.h
+++ b/src/stm32f4/internal.h
@@ -10,12 +10,12 @@
 
 #define GPIO_INPUT 0
 #define GPIO_OUTPUT 1
-#define GPIO_FUNCTION 2
+#define GPIO_FUNCTION(fn) (2 | ((fn) << 4))
 #define GPIO_ANALOG 3
 
 void enable_pclock(uint32_t periph_base);
 uint32_t get_pclock_frequency(uint32_t periph_base);
 void clock_setup(void);
-void gpio_peripheral(uint32_t gpio, uint32_t mode, uint32_t func, int pullup);
+void gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup);
 
 #endif // internal.h
diff --git a/src/stm32f4/serial.c b/src/stm32f4/serial.c
index 525e4493..f3087f4c 100644
--- a/src/stm32f4/serial.c
+++ b/src/stm32f4/serial.c
@@ -28,8 +28,8 @@ serial_init(void)
     NVIC_SetPriority(USART2_IRQn, 0);
     NVIC_EnableIRQ(USART2_IRQn);
 
-    gpio_peripheral(GPIO('A', 2), GPIO_FUNCTION, 7, 0);
-    gpio_peripheral(GPIO('A', 3), GPIO_FUNCTION, 7, 1);
+    gpio_peripheral(GPIO('A', 2), GPIO_FUNCTION(7), 0);
+    gpio_peripheral(GPIO('A', 3), GPIO_FUNCTION(7), 1);
 }
 DECL_INIT(serial_init);
 
diff --git a/src/stm32f4/spi.c b/src/stm32f4/spi.c
index 3759f286..a7e96874 100644
--- a/src/stm32f4/spi.c
+++ b/src/stm32f4/spi.c
@@ -20,9 +20,9 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
 
     // Enable SPI
     enable_pclock(SPI2_BASE);
-    gpio_peripheral(GPIO('B', 14), GPIO_FUNCTION, 5, 1);
-    gpio_peripheral(GPIO('B', 15), GPIO_FUNCTION, 5, 0);
-    gpio_peripheral(GPIO('B', 13), GPIO_FUNCTION, 5, 0);
+    gpio_peripheral(GPIO('B', 14), GPIO_FUNCTION(5), 1);
+    gpio_peripheral(GPIO('B', 15), GPIO_FUNCTION(5), 0);
+    gpio_peripheral(GPIO('B', 13), GPIO_FUNCTION(5), 0);
 
     // Calculate CR1 register
     uint32_t pclk = get_pclock_frequency(SPI2_BASE);