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stm32f4: Make using the internal clock source a low level option 

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2019-07-28 22:42:41 -04:00
parent 9bc3a29ee4
commit e6ffef9a9f
2 changed files with 11 additions and 7 deletions
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10
src/stm32f4/Kconfig
View File

@ -50,12 +50,16 @@ config STACK_SIZE
default 512 default 512
choice choice
prompt "Clock Reference" prompt "Clock Reference" if LOW_LEVEL_OPTIONS
config STM32F4_CLOCK_REF_8M config STM32_CLOCK_REF_8M
bool "8Mhz crystal" bool "8Mhz crystal"
config STM32F4_CLOCK_REF_INTERNAL config STM32_CLOCK_REF_INTERNAL
bool "Internal clock" bool "Internal clock"
endchoice endchoice
config CLOCK_REF_8M
bool
default n if STM32_CLOCK_REF_INTERNAL
default y
config SERIAL config SERIAL
bool bool

8
src/stm32f4/clock.c
View File

@ -4,7 +4,7 @@
// //
// This file may be distributed under the terms of the GNU GPLv3 license. // This file may be distributed under the terms of the GNU GPLv3 license.
#include "autoconf.h" // CONFIG_STM32F4_CLOCK_REF_8M #include "autoconf.h" // CONFIG_CLOCK_REF_8M
#include "command.h" // DECL_CONSTANT_STR #include "command.h" // DECL_CONSTANT_STR
#include "internal.h" // enable_pclock #include "internal.h" // enable_pclock
@ -76,7 +76,7 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift); regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift);
} }
#if CONFIG_STM32F4_CLOCK_REF_8M #if CONFIG_CLOCK_REF_8M
DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1"); DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
#endif #endif
@ -85,7 +85,7 @@ static void
enable_clock_stm32f40x(void) enable_clock_stm32f40x(void)
{ {
#if CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407 #if CONFIG_MACH_STM32F405 || CONFIG_MACH_STM32F407
if (CONFIG_STM32F4_CLOCK_REF_8M) { if (CONFIG_CLOCK_REF_8M) {
// Configure 168Mhz PLL from external 8Mhz crystal (HSE) // Configure 168Mhz PLL from external 8Mhz crystal (HSE)
RCC->CR |= RCC_CR_HSEON; RCC->CR |= RCC_CR_HSEON;
RCC->PLLCFGR = ( RCC->PLLCFGR = (
@ -107,7 +107,7 @@ static void
enable_clock_stm32f446(void) enable_clock_stm32f446(void)
{ {
#if CONFIG_MACH_STM32F446 #if CONFIG_MACH_STM32F446
if (CONFIG_STM32F4_CLOCK_REF_8M) { if (CONFIG_CLOCK_REF_8M) {
// Configure 180Mhz PLL from external 8Mhz crystal (HSE) // Configure 180Mhz PLL from external 8Mhz crystal (HSE)
RCC->CR |= RCC_CR_HSEON; RCC->CR |= RCC_CR_HSEON;
RCC->PLLCFGR = ( RCC->PLLCFGR = (