atsam: Add support for CAN on atsame70 (#6366)
Signed-off-by: Luke Vuksta <wulfstawulfsta@gmail.com>
This commit is contained in:
Luke V
GitHub
parent
b1f597c550
commit
dd01e99c59
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@ -50,6 +50,9 @@ config MACH_SAM4E
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select MACH_SAM4
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config MACH_SAME70
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bool
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config HAVE_SAM_CANBUS
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bool
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default y if MACH_SAME70
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config MCU
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string
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@ -101,6 +104,32 @@ choice
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config ATSAM_SERIAL
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bool "Serial"
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select SERIAL
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config ATSAM_MMENU_CANBUS_PC12_PD12
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bool "CAN bus (on PC12/PD12)"
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depends on HAVE_SAM_CANBUS
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select CANSERIAL
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config ATSAM_MMENU_CANBUS_PB3_PB2
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bool "CAN bus (on PB3/PB2)"
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depends on HAVE_SAM_CANBUS
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select CANSERIAL
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config ATSAM_USBCANBUS
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bool "USB to CAN bus bridge"
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depends on HAVE_SAM_CANBUS
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select USBCANBUS
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endchoice
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choice
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prompt "CAN bus interface" if USBCANBUS
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config ATSAM_CMENU_CANBUS_PC12_PD12
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bool "CAN bus (on PC12/PD12)"
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config ATSAM_CMENU_CANBUS_PB3_PB2
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bool "CAN bus (on PB3/PB2)"
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endchoice
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config ATSAM_CANBUS_PC12_PD12
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bool
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default y if ATSAM_MMENU_CANBUS_PC12_PD12 || ATSAM_CMENU_CANBUS_PC12_PD12
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config ATSAM_CANBUS_PB3_PB2
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bool
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default y if ATSAM_MMENU_CANBUS_PB3_PB2 || ATSAM_CMENU_CANBUS_PB3_PB2
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endif
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@ -3,7 +3,7 @@
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# Setup the toolchain
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CROSS_PREFIX=arm-none-eabi-
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dirs-y += src/atsam src/generic
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dirs-y += src/atsam src/generic lib/fast-hash
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dirs-$(CONFIG_MACH_SAM3X) += lib/sam3x/gcc
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dirs-$(CONFIG_MACH_SAM4S) += lib/sam4s/gcc
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dirs-$(CONFIG_MACH_SAM4E) += lib/sam4e/gcc
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@ -18,7 +18,7 @@ CFLAGS-$(CONFIG_MACH_SAM3X) += -Ilib/sam3x/include
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CFLAGS-$(CONFIG_MACH_SAM4S) += -Ilib/sam4s/include
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CFLAGS-$(CONFIG_MACH_SAM4E) += -Ilib/sam4e/include
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CFLAGS-$(CONFIG_MACH_SAME70) += -Ilib/same70b/include
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CFLAGS += $(CFLAGS-y) -D__$(MCU)__ -mthumb -Ilib/cmsis-core
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CFLAGS += $(CFLAGS-y) -D__$(MCU)__ -mthumb -Ilib/cmsis-core -Ilib/fast-hash
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CFLAGS_klipper.elf += --specs=nano.specs --specs=nosys.specs
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CFLAGS_klipper.elf += -T $(OUT)src/generic/armcm_link.ld
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@ -33,6 +33,10 @@ usb-src-$(CONFIG_MACH_SAM4) := atsam/sam4_usb.c
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usb-src-$(CONFIG_MACH_SAME70) := atsam/sam3_usb.c
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src-$(CONFIG_USBSERIAL) += $(usb-src-y) atsam/chipid.c generic/usb_cdc.c
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src-$(CONFIG_SERIAL) += atsam/serial.c generic/serial_irq.c
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canbus-src-y := generic/canserial.c ../lib/fast-hash/fasthash.c
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canbus-src-y += atsam/fdcan.c atsam/chipid.c
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src-$(CONFIG_USBCANBUS) += $(canbus-src-y) $(usb-src-y) generic/usb_canbus.c
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src-$(CONFIG_CANSERIAL) += $(canbus-src-y) generic/canbus.c
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src-$(CONFIG_MACH_SAM3X) += atsam/adc.c atsam/hard_pwm.c
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src-$(CONFIG_MACH_SAM4) += atsam/hard_pwm.c
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src-$(CONFIG_MACH_SAM4S) += atsam/adc.c
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@ -5,6 +5,7 @@
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "generic/irq.h" // irq_disable
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#include "generic/canserial.h" // canserial_set_uuid
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#include "generic/usb_cdc.h" // usb_fill_serial
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#include "generic/usbstd.h" // usb_string_descriptor
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#include "internal.h" // EFC0
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@ -61,7 +62,7 @@ read_chip_id(uint32_t *id)
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void
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chipid_init(void)
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{
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if (!CONFIG_USB_SERIAL_NUMBER_CHIPID)
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if (!CONFIG_USB_SERIAL_NUMBER_CHIPID && !CONFIG_CANBUS)
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return;
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uint32_t id[4];
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@ -69,6 +70,10 @@ chipid_init(void)
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read_chip_id(id);
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irq_enable();
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if (CONFIG_USB_SERIAL_NUMBER_CHIPID)
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usb_fill_serial(&cdc_chipid.desc, ARRAY_SIZE(cdc_chipid.data), id);
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if (CONFIG_CANBUS)
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canserial_set_uuid((void*)id, CHIP_UID_LEN);
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}
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DECL_INIT(chipid_init);
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@ -0,0 +1,307 @@
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// CANbus support on atsame70 chips
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//
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// Copyright (C) 2021-2022 Kevin O'Connor <kevin@koconnor.net>
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// Copyright (C) 2019 Eug Krashtan <eug.krashtan@gmail.com>
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// Copyright (C) 2020 Pontus Borg <glpontus@gmail.com>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "command.h" // DECL_CONSTANT_STR
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#include "generic/armcm_boot.h" // armcm_enable_irq
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#include "generic/canbus.h" // canbus_notify_tx
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#include "generic/canserial.h" // CANBUS_ID_ADMIN
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#include "internal.h" // enable_pclock
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#include "sched.h" // DECL_INIT
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/****************************************************************
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* Pin configuration
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****************************************************************/
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#if CONFIG_ATSAM_CANBUS_PB3_PB2
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PB3,PB2");
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#define GPIO_Rx GPIO('B', 3)
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#define GPIO_Tx GPIO('B', 2)
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#define CANx_GCLK_ID MCAN0_CLOCK_ID
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#elif CONFIG_ATSAM_CANBUS_PC12_PD12
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DECL_CONSTANT_STR("RESERVE_PINS_CAN", "PC12,PD12");
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#define GPIO_Rx GPIO('C', 12)
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#define GPIO_Tx GPIO('D', 12)
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#define CANx_GCLK_ID MCAN1_CLOCK_ID
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#endif
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#if CANx_GCLK_ID == MCAN0_CLOCK_ID
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#define CAN_FUNCTION_Rx 'A'
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#define CAN_FUNCTION_Tx 'A'
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#define CANx MCAN0
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#define CANx_IRQn MCAN0_INT0_IRQn
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#define CCFG_CANxDMABA MATRIX->CCFG_CAN0
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#define CCFG_CANxDMABA_Msk CCFG_CAN0_CAN0DMABA_Msk
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#define CCFG_CANxDMABA_Pos CCFG_CAN0_CAN0DMABA_Pos
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#else
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#define CAN_FUNCTION_Rx 'C'
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#define CAN_FUNCTION_Tx 'B'
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#define CANx MCAN1
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#define CANx_IRQn MCAN1_INT0_IRQn
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#define CCFG_CANxDMABA MATRIX->CCFG_SYSIO
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#define CCFG_CANxDMABA_Msk CCFG_SYSIO_CAN1DMABA_Msk
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#define CCFG_CANxDMABA_Pos CCFG_SYSIO_CAN1DMABA_Pos
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#endif
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/****************************************************************
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* Message ram layout
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****************************************************************/
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struct fdcan_fifo {
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uint32_t id_section;
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uint32_t dlc_section;
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uint32_t data[64 / 4];
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};
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#define FDCAN_XTD (1<<30)
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#define FDCAN_RTR (1<<29)
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struct fdcan_msg_ram {
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uint32_t FLS[28]; // Filter list standard
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uint32_t FLE[16]; // Filter list extended
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struct fdcan_fifo RXF0[3];
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struct fdcan_fifo RXF1[3];
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uint32_t TEF[6]; // Tx event FIFO
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struct fdcan_fifo TXFIFO[3];
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};
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// Message ram is in regular memory
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static struct fdcan_msg_ram MSG_RAM;
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/****************************************************************
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* CANbus code
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****************************************************************/
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#define FDCAN_IE_TC (MCAN_IE_TCE | MCAN_IE_TCFE | MCAN_IE_TFEE)
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// Transmit a packet
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int
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canhw_send(struct canbus_msg *msg)
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{
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uint32_t txfqs = CANx->MCAN_TXFQS;
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if (txfqs & MCAN_TXFQS_TFQF)
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// No space in transmit fifo - wait for irq
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return -1;
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uint32_t w_index = ((txfqs & MCAN_TXFQS_TFQPI_Msk) >> MCAN_TXFQS_TFQPI_Pos);
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struct fdcan_fifo *txfifo = &MSG_RAM.TXFIFO[w_index];
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uint32_t ids;
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if (msg->id & CANMSG_ID_EFF)
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ids = (msg->id & 0x1fffffff) | FDCAN_XTD;
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else
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ids = (msg->id & 0x7ff) << 18;
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ids |= msg->id & CANMSG_ID_RTR ? FDCAN_RTR : 0;
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txfifo->id_section = ids;
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txfifo->dlc_section = (msg->dlc & 0x0f) << 16;
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txfifo->data[0] = msg->data32[0];
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txfifo->data[1] = msg->data32[1];
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__DMB();
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CANx->MCAN_TXBAR;
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CANx->MCAN_TXBAR = ((uint32_t)1 << w_index);
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return CANMSG_DATA_LEN(msg);
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}
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static void
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can_filter(uint32_t index, uint32_t id)
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{
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MSG_RAM.FLS[index] = ((0x2 << 30) // Classic filter
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| (0x1 << 27) // Store in Rx FIFO 0 if filter matches
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| (id << 16)
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| 0x7FF); // mask all enabled
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}
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// Setup the receive packet filter
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void
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canhw_set_filter(uint32_t id)
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{
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if (!CONFIG_CANBUS_FILTER)
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return;
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/* Request initialisation */
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CANx->MCAN_CCCR |= MCAN_CCCR_INIT;
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/* Wait the acknowledge */
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while (!(CANx->MCAN_CCCR & MCAN_CCCR_INIT))
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;
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/* Enable configuration change */
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CANx->MCAN_CCCR |= MCAN_CCCR_CCE;
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// Load filter
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can_filter(0, CANBUS_ID_ADMIN);
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can_filter(1, id);
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can_filter(2, id + 1);
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uint32_t flssa = (uint32_t)MSG_RAM.FLS
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- (CCFG_CANxDMABA_Msk & CCFG_CANxDMABA);
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CANx->MCAN_SIDFC = flssa | ((id ? 3 : 1) << MCAN_SIDFC_LSS_Pos);
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CANx->MCAN_GFC = 0x02 << MCAN_GFC_ANFS_Pos;
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/* Leave the initialisation mode for the filter */
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barrier();
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CANx->MCAN_CCCR &= ~MCAN_CCCR_CCE;
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CANx->MCAN_CCCR &= ~MCAN_CCCR_INIT;
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}
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// This function handles CAN global interrupts
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void
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CAN_IRQHandler(void)
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{
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uint32_t ir = CANx->MCAN_IR;
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if (ir & MCAN_IE_RF0NE) {
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CANx->MCAN_IR = MCAN_IE_RF0NE;
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uint32_t rxf0s = CANx->MCAN_RXF0S;
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if (rxf0s & MCAN_RXF0S_F0FL_Msk) {
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// Read and ack data packet
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uint32_t idx = (rxf0s & MCAN_RXF0S_F0GI_Msk) >> MCAN_RXF0S_F0GI_Pos;
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struct fdcan_fifo *rxf0 = &MSG_RAM.RXF0[idx];
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uint32_t ids = rxf0->id_section;
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struct canbus_msg msg;
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if (ids & FDCAN_XTD)
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msg.id = (ids & 0x1fffffff) | CANMSG_ID_EFF;
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else
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msg.id = (ids >> 18) & 0x7ff;
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msg.id |= ids & FDCAN_RTR ? CANMSG_ID_RTR : 0;
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msg.dlc = (rxf0->dlc_section >> 16) & 0x0f;
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msg.data32[0] = rxf0->data[0];
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msg.data32[1] = rxf0->data[1];
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barrier();
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CANx->MCAN_RXF0A = idx;
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// Process packet
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canbus_process_data(&msg);
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}
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}
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if (ir & FDCAN_IE_TC) {
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// Tx
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CANx->MCAN_IR = FDCAN_IE_TC;
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canbus_notify_tx();
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}
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}
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static inline const uint32_t
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make_btr(uint32_t sjw, // Sync jump width, ... hmm
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uint32_t time_seg1, // time segment before sample point, 1 .. 16
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uint32_t time_seg2, // time segment after sample point, 1 .. 8
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uint32_t brp) // Baud rate prescaler, 1 .. 1024
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{
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return (((uint32_t)(sjw-1)) << MCAN_NBTP_NSJW_Pos
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| ((uint32_t)(time_seg1-1)) << MCAN_NBTP_NTSEG1_Pos
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| ((uint32_t)(time_seg2-1)) << MCAN_NBTP_NTSEG2_Pos
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| ((uint32_t)(brp - 1)) << MCAN_NBTP_NBRP_Pos);
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}
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static inline const uint32_t
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compute_btr(uint32_t pclock, uint32_t bitrate)
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{
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/*
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Some equations:
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Tpclock = 1 / pclock
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Tq = brp * Tpclock
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Tbs1 = Tq * TS1
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Tbs2 = Tq * TS2
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NominalBitTime = Tq + Tbs1 + Tbs2
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BaudRate = 1/NominalBitTime
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Bit value sample point is after Tq+Tbs1. Ideal sample point
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is at 87.5% of NominalBitTime
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Use the lowest brp where ts1 and ts2 are in valid range
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*/
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uint32_t bit_clocks = pclock / bitrate; // clock ticks per bit
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uint32_t sjw = 2;
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uint32_t qs;
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// Find number of time quantas that gives us the exact wanted bit time
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for (qs = 18; qs > 9; qs--) {
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// check that bit_clocks / quantas is an integer
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uint32_t brp_rem = bit_clocks % qs;
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if (brp_rem == 0)
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break;
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}
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uint32_t brp = bit_clocks / qs;
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uint32_t time_seg2 = qs / 8; // sample at ~87.5%
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uint32_t time_seg1 = qs - (1 + time_seg2);
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return make_btr(sjw, time_seg1, time_seg2, brp);
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}
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void
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can_init(void)
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{
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if (!CONFIG_USBCANBUS) {
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// Configure UPLL for USB and CAN
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PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(3) | CKGR_UCKR_UPLLEN;
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while (!(PMC->PMC_SR & PMC_SR_LOCKU))
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;
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}
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// Configure PCK5 for CAN use
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PMC->PMC_PCK[5] = PMC_PCK_CSS_UPLL_CLK | PMC_PCK_PRES(5);
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while (!(PMC->PMC_SR & PMC_SR_PCKRDY5))
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;
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PMC->PMC_SCER |= PMC_SCER_PCK5;
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enable_pclock(CANx_GCLK_ID);
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gpio_peripheral(GPIO_Rx, CAN_FUNCTION_Rx, 1);
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gpio_peripheral(GPIO_Tx, CAN_FUNCTION_Tx, 0);
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uint32_t pclock = get_pclock_frequency(CANx_GCLK_ID);
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uint32_t btr = compute_btr(pclock, CONFIG_CANBUS_FREQUENCY);
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/*##-1- Configure the CAN #######################################*/
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/* Exit from sleep mode */
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CANx->MCAN_CCCR &= ~MCAN_CCCR_CSR;
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/* Wait the acknowledge */
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while (CANx->MCAN_CCCR & MCAN_CCCR_CSA)
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;
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/* Request initialization */
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CANx->MCAN_CCCR |= MCAN_CCCR_INIT;
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/* Wait the acknowledge */
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while (!(CANx->MCAN_CCCR & MCAN_CCCR_INIT))
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;
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/* Enable configuration change */
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CANx->MCAN_CCCR |= MCAN_CCCR_CCE;
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/* Disable protocol exception handling */
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CANx->MCAN_CCCR |= MCAN_CCCR_PXHD;
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CANx->MCAN_NBTP = btr;
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/* Setup message RAM addresses */
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uint32_t ccfg = (CCFG_CANxDMABA & ~CCFG_CANxDMABA_Msk);
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CCFG_CANxDMABA = (ccfg | (((uint32_t)&MSG_RAM)
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& CCFG_CANxDMABA_Msk));
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uint32_t f0sa = (uint32_t)MSG_RAM.RXF0
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- (CCFG_CANxDMABA_Msk & CCFG_CANxDMABA);
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CANx->MCAN_RXF0C = f0sa
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| (ARRAY_SIZE(MSG_RAM.RXF0) << MCAN_RXF0C_F0S_Pos);
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CANx->MCAN_RXESC = (7 << MCAN_RXESC_F1DS_Pos)
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| (7 << MCAN_RXESC_F0DS_Pos);
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uint32_t tbsa = (uint32_t)MSG_RAM.TXFIFO
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- (CCFG_CANxDMABA_Msk & CCFG_CANxDMABA);
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CANx->MCAN_TXBC = tbsa
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| (ARRAY_SIZE(MSG_RAM.TXFIFO) << MCAN_TXBC_TFQS_Pos);
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CANx->MCAN_TXESC = 7 << MCAN_TXESC_TBDS_Pos;
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/* Leave the initialisation mode */
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CANx->MCAN_CCCR &= ~MCAN_CCCR_CCE;
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CANx->MCAN_CCCR &= ~MCAN_CCCR_INIT;
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/*##-2- Configure the CAN Filter #######################################*/
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canhw_set_filter(0);
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/*##-3- Configure Interrupts #################################*/
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armcm_enable_irq(CAN_IRQHandler, CANx_IRQn, 1);
|
||||
CANx->MCAN_ILE = MCAN_ILE_EINT0;
|
||||
CANx->MCAN_IE = MCAN_IE_RF0NE | FDCAN_IE_TC;
|
||||
}
|
||||
DECL_INIT(can_init);
|
||||
|
|
@ -14,6 +14,8 @@
|
|||
#define FREQ_PERIPH_DIV (CONFIG_MACH_SAME70 ? 2 : 1)
|
||||
#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / FREQ_PERIPH_DIV)
|
||||
|
||||
#define FREQ_SAME70_CAN 80000000
|
||||
|
||||
/****************************************************************
|
||||
* watchdog handler
|
||||
****************************************************************/
|
||||
|
|
@ -62,6 +64,10 @@ enable_pclock(uint32_t id)
|
|||
uint32_t
|
||||
get_pclock_frequency(uint32_t id)
|
||||
{
|
||||
#if CONFIG_MACH_SAME70
|
||||
if (id == MCAN0_CLOCK_ID || id == MCAN1_CLOCK_ID)
|
||||
return FREQ_SAME70_CAN;
|
||||
#endif
|
||||
return FREQ_PERIPH;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -70,5 +70,8 @@ void SystemInit( void )
|
|||
|
||||
// Configure PCK6 for TC use
|
||||
PMC->PMC_PCK[6] = PMC_PCK_CSS_MCK | PMC_PCK_PRES(2);
|
||||
PMC->PMC_SCER = PMC_SCER_PCK6;
|
||||
while ( !(PMC->PMC_SR & PMC_SR_PCKRDY6) )
|
||||
{
|
||||
}
|
||||
PMC->PMC_SCER |= PMC_SCER_PCK6;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue