samd21: Add support for SPI

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>

src/samd21/Kconfig

@@ -7,6 +7,7 @@ config SAMD_SELECT
     default y
     select HAVE_GPIO
     select HAVE_GPIO_I2C
+    select HAVE_GPIO_SPI
     select HAVE_GPIO_BITBANGING
 
 config BOARD_DIRECTORY

src/samd21/Makefile

@@ -21,6 +21,7 @@ src-y += ../lib/samd21/samd21a/gcc/gcc/startup_samd21.c
 src-$(CONFIG_USBSERIAL) += samd21/usbserial.c generic/usb_cdc.c
 src-$(CONFIG_SERIAL) += samd21/serial.c generic/serial_irq.c
 src-$(CONFIG_HAVE_GPIO_I2C) += samd21/i2c.c
+src-$(CONFIG_HAVE_GPIO_SPI) += samd21/spi.c
 
 # Support bootloader offset address
 target-y := $(OUT)samd21.ld $(target-y)

src/samd21/gpio.h

@@ -21,6 +21,14 @@ struct gpio_in gpio_in_setup(uint8_t pin, int8_t pull_up);
 void gpio_in_reset(struct gpio_in g, int8_t pull_up);
 uint8_t gpio_in_read(struct gpio_in g);
 
+struct spi_config {
+    uint32_t ctrla, baud;
+};
+struct spi_config spi_setup(uint32_t bus, uint8_t mode, uint32_t rate);
+void spi_prepare(struct spi_config config);
+void spi_transfer(struct spi_config config, uint8_t receive_data
+                  , uint8_t len, uint8_t *data);
+
 struct i2c_config {
     uint8_t addr;
 };

src/samd21/spi.c

@@ -0,0 +1,92 @@
+// spi support on samd21
+//
+// Copyright (C) 2018  Kevin O'Connor <kevin@koconnor.net>
+//
+// This file may be distributed under the terms of the GNU GPLv3 license.
+
+#include "autoconf.h" // CONFIG_CLOCK_FREQ
+#include "internal.h" // enable_pclock
+#include "command.h" // shutdown
+#include "gpio.h" // spi_setup
+#include "samd21.h" // SERCOM4
+#include "sched.h" // sched_shutdown
+
+static void
+spi_init(uint32_t ctrla, uint32_t baud)
+{
+    static int have_run_init;
+    if (have_run_init)
+        return;
+    have_run_init = 1;
+
+    // Setup clock
+    enable_pclock(SERCOM4_GCLK_ID_CORE, PM_APBCMASK_SERCOM4);
+
+    // Configure MISO, MOSI, SCK pins
+    gpio_peripheral(GPIO('A', 12), 'D', 0);
+    gpio_peripheral(GPIO('B', 10), 'D', 0);
+    gpio_peripheral(GPIO('B', 11), 'D', 0);
+
+    // Configure spi
+    SercomSpi *ss = &SERCOM4->SPI;
+    ss->CTRLA.reg = 0;
+    ss->CTRLA.reg = ctrla & ~SERCOM_SPI_CTRLA_ENABLE;
+    ss->CTRLB.reg = SERCOM_SPI_CTRLB_RXEN;
+    ss->BAUD.reg = baud;
+    ss->CTRLA.reg = ctrla;
+}
+
+struct spi_config
+spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
+{
+    if (bus)
+        shutdown("Invalid spi bus");
+
+    uint32_t ctrla = (SERCOM_SPI_CTRLA_MODE_SPI_MASTER
+                      | (mode << SERCOM_SPI_CTRLA_CPHA_Pos)
+                      | SERCOM_SPI_CTRLA_DIPO(0)
+                      | SERCOM_SPI_CTRLA_DOPO(1)
+                      | SERCOM_SPI_CTRLA_ENABLE);
+    uint32_t baud = CONFIG_CLOCK_FREQ / (2 * rate) - 1;
+    spi_init(ctrla, baud);
+    return (struct spi_config){ .ctrla = ctrla, .baud = baud };
+}
+
+void
+spi_prepare(struct spi_config config)
+{
+    uint32_t ctrla = config.ctrla, baud = config.baud;
+    SercomSpi *ss = &SERCOM4->SPI;
+    if (ctrla == ss->CTRLA.reg && baud == ss->BAUD.reg)
+        return;
+    ss->CTRLA.reg = ctrla & ~SERCOM_SPI_CTRLA_ENABLE;
+    ss->CTRLA.reg = ctrla & ~SERCOM_SPI_CTRLA_ENABLE;
+    ss->BAUD.reg = baud;
+    ss->CTRLA.reg = ctrla;
+}
+
+void
+spi_transfer(struct spi_config config, uint8_t receive_data
+             , uint8_t len, uint8_t *data)
+{
+    SercomSpi *ss = &SERCOM4->SPI;
+    if (receive_data) {
+        while (len--) {
+            ss->DATA.reg = *data;
+            // wait for receive register
+            while (!(ss->INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC))
+                ;
+            // get data
+            *data++ = ss->DATA.reg;
+        }
+    } else {
+        while (len--) {
+            ss->DATA.reg = *data++;
+            // wait for receive register
+            while (!(ss->INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC))
+                ;
+            // read data (to clear RXC)
+            ss->DATA.reg;
+        }
+    }
+}