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stm32: Move clock line mapping from stm32h7_adc.c to lookup_clock_line() 

Use the common lookup_clock_line() code to lookup the adc clock lines.
This also enables resets on the adc1/adc2 hardware block.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2022-12-13 12:36:26 -05:00
parent 1034f19134
commit cef0b70c88
4 changed files with 14 additions and 17 deletions
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4
src/stm32/stm32g4.c
View File

@ -43,6 +43,10 @@ lookup_clock_line(uint32_t periph_base)
.bit = 1 << pos};
} else {
if (periph_base == ADC12_COMMON_BASE)
return (struct cline){.en = &RCC->AHB2ENR,
.rst = &RCC->AHB2RSTR,
.bit = RCC_AHB2ENR_ADC12EN};
uint32_t pos = (periph_base - AHB2PERIPH_BASE) / 0x400;
return (struct cline){.en = &RCC->AHB2ENR,
.rst = &RCC->AHB2RSTR,

3
src/stm32/stm32h7.c
View File

@ -40,6 +40,9 @@ lookup_clock_line(uint32_t periph_base)
uint32_t bit = 1 << ((periph_base - D2_AHB2PERIPH_BASE) / 0x400);
return (struct cline){.en=&RCC->AHB2ENR, .rst=&RCC->AHB2RSTR, .bit=bit};
} else if (periph_base >= D2_AHB1PERIPH_BASE) {
if (periph_base == ADC12_COMMON_BASE)
return (struct cline){.en = &RCC->AHB1ENR, .rst = &RCC->AHB1RSTR,
.bit = RCC_AHB1ENR_ADC12EN};
uint32_t bit = 1 << ((periph_base - D2_AHB1PERIPH_BASE) / 0x400);
return (struct cline){.en=&RCC->AHB1ENR, .rst=&RCC->AHB1RSTR, .bit=bit};
} else if (periph_base >= D2_APB2PERIPH_BASE) {

18
src/stm32/stm32h7_adc.c
View File

@ -1,34 +1,27 @@
// ADC functions on STM32H7
// Analog to digital (ADC) on stm32h7 and similar chips
//
// Copyright (C) 2020 Konstantin Vogel <konstantin.vogel@gmx.net>
// Copyright (C) 2022 Kevin O'Connor <kevin@koconnor.net>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
#include "board/irq.h" // irq_save
#include "board/misc.h" // timer_from_us
#include "command.h" // shutdown
#include "compiler.h" // ARRAY_SIZE
#include "generic/armcm_timer.h" // udelay
#include "gpio.h" // gpio_adc_setup
#include "internal.h" // GPIO
#include "sched.h" // sched_shutdown
#if CONFIG_MACH_STM32H7
#define RCC_AHBENR_ADC (RCC->AHB1ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB1ENR_ADC12EN)
#define ADC_CKMODE (0b11)
#define ADC_ATICKS (0b101)
#if CONFIG_MACH_STM32H723
#define PCSEL PCSEL_RES0
#endif
#elif CONFIG_MACH_STM32L4
#define RCC_AHBENR_ADC (RCC->AHB2ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADCEN)
#define ADC_CKMODE (0)
#define ADC_ATICKS (0b100)
#elif CONFIG_MACH_STM32G4
#define RCC_AHBENR_ADC (RCC->AHB2ENR)
#define RCC_AHBENR_ADCEN (RCC_AHB2ENR_ADC12EN)
#define ADC_CKMODE (0b11)
#define ADC_ATICKS (0b100)
#define ADC_CCR_TSEN (ADC_CCR_VSENSESEL)
@ -202,9 +195,6 @@ gpio_adc_setup(uint32_t pin)
chan -= 2 * ADCIN_BANK_SIZE;
adc = ADC3;
adc_common = ADC3_COMMON;
if (!is_enabled_pclock(ADC3_BASE)) {
enable_pclock(ADC3_BASE);
}
} else
#endif
#ifdef ADC2
@ -212,14 +202,14 @@ gpio_adc_setup(uint32_t pin)
chan -= ADCIN_BANK_SIZE;
adc = ADC2;
adc_common = ADC12_COMMON;
RCC_AHBENR_ADC |= RCC_AHBENR_ADCEN;
} else
#endif
{
adc = ADC1;
adc_common = ADC12_COMMON;
RCC_AHBENR_ADC |= RCC_AHBENR_ADCEN;
}
if (!is_enabled_pclock((uint32_t)adc_common))
enable_pclock((uint32_t)adc_common);
MODIFY_REG(adc_common->CCR, ADC_CCR_CKMODE_Msk,
ADC_CKMODE << ADC_CCR_CKMODE_Pos);

2
src/stm32/stm32l4.c
View File

@ -42,7 +42,7 @@ lookup_clock_line(uint32_t periph_base)
.rst = &RCC->AHB1RSTR,
.bit = 1 << pos};
} else if (periph_base == ADC1_BASE) {
} else if (periph_base == ADC12_COMMON_BASE) {
return (struct cline){.en = &RCC->AHB2ENR,
.rst = &RCC->AHB2RSTR,
.bit = RCC_AHB2ENR_ADCEN};