pru: Add initial pru_rpmsg library code for Beaglebone PRU
Add external code for using RPMsg on the Beaglebone PRU. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
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lib/README
12
lib/README
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@ -7,10 +7,16 @@ on recent versions of gcc. See usb_serial.patch for the modifications.
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The cmsis-sam3x8e directory contains code from the Arduino project:
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https://www.arduino.cc/
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version 1.5.1 (extracted on 20160608). It has been modified to
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compile with gcc's LTO feature. See cmsis-sam3x8e.patch for the
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modifications.
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version 1.5.1 (extracted on 20160608). It has been modified to compile
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with gcc's LTO feature. See cmsis-sam3x8e.patch for the modifications.
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The hub-ctrl directory contains code from:
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https://github.com/codazoda/hub-ctrl.c/
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revision 42095e522859059e8a5f4ec05c1e3def01a870a9.
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The pru_rpmsg directory contains code from:
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https://github.com/dinuxbg/pru-gcc-examples
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revision 425a42d82006cf0aa24be27b483d2f6a41607489. The code is taken
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from the repo's hc-sr04-range-sensor directory. It has been modified
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so that the IEP definitions compile correctly. See pru_rpmsg.patch for
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the modifications.
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@ -0,0 +1,25 @@
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Programmable Real-time Unit (PRU) Software Support Package
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------------------------------------------------------------
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============================================================
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INCLUDE
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============================================================
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DESCRIPTION
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This directory provides header files for PRU firmware.
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For more details about these header files, visit:
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http://processors.wiki.ti.com/index.php/PRU-ICSS_Header_Files
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ADDITIONAL RESOURCES
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For more information about the PRU, visit:
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PRU-ICSS Wiki - http://processors.wiki.ti.com/index.php/PRU-ICSS
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PRU Training Slides - http://www.ti.com/sitarabootcamp
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PRU Evaluation Hardware - http://www.ti.com/tool/PRUCAPE
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Support - http://e2e.ti.com
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@ -0,0 +1,249 @@
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/*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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||||
* * Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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*
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||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the
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* distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _PRU_CFG_H_
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#define _PRU_CFG_H_
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/* PRU_CFG register set */
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typedef struct {
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/* PRU_CFG_REVID register bit field */
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union {
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volatile uint32_t REVID;
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volatile struct {
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unsigned REVID : 32;
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} REVID_bit;
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}; // 0x0
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/* PRU_CFG_SYSCFG register bit field */
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union {
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volatile uint32_t SYSCFG;
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volatile struct {
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unsigned IDLE_MODE : 2;
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unsigned STANDBY_MODE : 2;
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unsigned STANDBY_INIT : 1;
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unsigned SUB_MWAIT : 1;
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unsigned rsvd6 : 26;
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} SYSCFG_bit;
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}; // 0x4
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/* PRU_CFG_GPCFG0 register bit field */
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union {
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volatile uint32_t GPCFG0;
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volatile struct {
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unsigned PRU0_GPI_MODE : 2; // 1:0
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unsigned PRU0_GPI_CLK_MODE : 1; // 2
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unsigned PRU0_GPI_DIV0 : 5; // 7:3
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unsigned PRU0_GPI_DIV1 : 5; // 12:8
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unsigned PRU0_GPI_SB : 1; // 13
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unsigned PRU0_GPO_MODE : 1; // 14
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unsigned PRU0_GPO_DIV0 : 5; // 19:15
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unsigned PRU0_GPO_DIV1 : 5; // 24:20
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unsigned PRU0_GPO_SH_SEL : 1; // 25
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unsigned rsvd26 : 6; // 31:26
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} GPCFG0_bit;
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}; // 0x8
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/* PRU_CFG_GPCFG1 register bit field */
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union {
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volatile uint32_t GPCFG1;
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volatile struct {
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unsigned PRU1_GPI_MODE : 2; // 1:0
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unsigned PRU1_GPI_CLK_MODE : 1; // 2
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unsigned PRU1_GPI_DIV0 : 5; // 7:3
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unsigned PRU1_GPI_DIV1 : 5; // 12:8
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unsigned PRU1_GPI_SB : 1; // 13
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unsigned PRU1_GPO_MODE : 1; // 14
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unsigned PRU1_GPO_DIV0 : 5; // 19:15
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unsigned PRU1_GPO_DIV1 : 5; // 24:20
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unsigned PRU1_GPO_SH_SEL : 1; // 25
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unsigned rsvd26 : 6; // 31:26
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} GPCFG1_bit;
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}; // 0xC
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/* PRU_CFG_CGR register bit field */
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union {
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volatile uint32_t CGR;
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volatile struct {
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unsigned PRU0_CLK_STOP_REQ : 1; // 0
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unsigned PRU0_CLK_STOP_ACK : 1; // 1
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unsigned PRU0_CLK_EN : 1; // 2
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unsigned PRU1_CLK_STOP_REQ : 1; // 3
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unsigned PRU1_CLK_STOP_ACK : 1; // 4
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unsigned PRU1_CLK_EN : 1; // 5
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unsigned INTC_CLK_STOP_REQ : 1; // 6
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unsigned INTC_CLK_STOP_ACK : 1; // 7
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unsigned INTC_CLK_EN : 1; // 8
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unsigned UART_CLK_STOP_REQ : 1; // 9
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unsigned UART_CLK_STOP_ACK : 1; // 10
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unsigned UART_CLK_EN : 1; // 11
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unsigned ECAP_CLK_STOP_REQ : 1; // 12
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unsigned ECAP_CLK_STOP_ACK : 1; // 13
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unsigned ECAP_CLK_EN : 1; // 14
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unsigned IEP_CLK_STOP_REQ : 1; // 15
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unsigned IEP_CLK_STOP_ACK : 1; // 16
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unsigned IEP_CLK_EN : 1; // 17
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unsigned rsvd18 : 14; // 31:18
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} CGR_bit;
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}; // 0x10
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/* PRU_CFG_ISRP register bit field */
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union {
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volatile uint32_t ISRP;
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volatile struct {
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unsigned PRU0_IMEM_PE_RAW : 4; // 3:0
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unsigned PRU0_DMEM_PE_RAW : 4; // 7:4
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unsigned PRU1_IMEM_PE_RAW : 4; // 11:8
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unsigned PRU1_DMEM_PE_RAW : 4; // 15:12
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unsigned RAM_PE_RAW : 4; // 19:16
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unsigned rsvd20 : 12; // 31:20
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} ISRP_bit;
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}; // 0x14
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/* PRU_CFG_ISP register bit field */
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union {
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volatile uint32_t ISP;
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volatile struct {
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unsigned PRU0_IMEM_PE : 4; // 3:0
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unsigned PRU0_DMEM_PE : 4; // 7:4
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unsigned PRU1_IMEM_PE : 4; // 11:8
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unsigned PRU1_DMEM_PE : 4; // 15:12
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unsigned RAM_PE : 4; // 19:16
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unsigned rsvd20 : 12; // 31:20
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} ISP_bit;
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}; // 0x18
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/* PRU_CFG_IESP register bit field */
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union {
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volatile uint32_t IESP;
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volatile struct {
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unsigned PRU0_IMEM_PE_SET : 4; // 3:0
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unsigned PRU0_DMEM_PE_SET : 4; // 7:4
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unsigned PRU1_IMEM_PE_SET : 4; // 11:8
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unsigned PRU1_DMEM_PE_SET : 4; // 15:12
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unsigned RAM_PE_SET : 4; // 19:16
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unsigned rsvd20 : 12; // 31:20
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} IESP_bit;
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}; // 0x1C
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/* PRU_CFG_IECP register bit field */
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union {
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volatile uint32_t IECP;
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volatile struct {
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unsigned PRU0_IMEM_PE_CLR : 4; // 3:0
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unsigned PRU0_DMEM_PE_CLR : 4; // 7:4
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unsigned PRU1_IMEM_PE_CLR : 4; // 11:8
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unsigned PRU1_DMEM_PE_CLR : 4; // 15:12
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unsigned rsvd16 : 16; // 31:16
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} IECP_bit;
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}; // 0x20
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uint32_t rsvd24; // 0x24
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/* PRU_CFG_PMAO register bit field */
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union {
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volatile uint32_t PMAO;
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volatile struct {
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unsigned PMAO_PRU0 : 1; // 0
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unsigned PMAO_PRU1 : 1; // 1
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unsigned rsvd2 : 30; // 31:2
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} PMAO_bit;
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}; // 0x28
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uint32_t rsvd2c[1]; // 0x2C
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/* PRU_CFG_IEPCLK register bit field */
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union {
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volatile uint32_t IEPCLK;
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volatile struct {
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unsigned OCP_EN : 1; // 0
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unsigned rsvd1 : 31; // 31:1
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} IEPCLK_bit;
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}; // 0x30
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/* PRU_CFG_SPP register bit field */
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union {
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volatile uint32_t SPP;
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volatile struct {
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unsigned PRU1_PAD_HP_EN : 1; // 0
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unsigned XFR_SHIFT_EN : 1; // 1
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unsigned rsvd2 : 30; // 31:2
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} SPP_bit;
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}; // 0x34
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uint32_t rsvd38[2]; // 0x38 - 0x3C
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union {
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volatile uint32_t PIN_MX;
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volatile struct {
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unsigned PIN_MUX_SEL : 8; // 7:0
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unsigned rsvd2 : 24; // 31:8
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} PIN_MX_bit;
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}; //0x40
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} pruCfg;
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#ifdef __GNUC__
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static volatile pruCfg *__CT_CFG = (void *)0x00026000;
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#define CT_CFG (*__CT_CFG)
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#else
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volatile __far pruCfg CT_CFG __attribute__((cregister("PRU_CFG", near), peripheral));
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#endif
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#endif /* _PRU_CFG_H_ */
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@ -0,0 +1,155 @@
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/*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
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* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
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* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _PRU_CTRL_H_
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#define _PRU_CTRL_H_
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/* PRU_CTRL register set */
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typedef struct {
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/* PRU_CTRL_CTRL register bit field */
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union {
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volatile uint32_t CTRL;
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volatile struct {
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unsigned SOFT_RST_N : 1;
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unsigned EN : 1;
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unsigned SLEEPING : 1;
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unsigned CTR_EN : 1;
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unsigned rsvd4 : 4;
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unsigned SINGLE_STEP : 1;
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unsigned rsvd9 : 6;
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unsigned RUNSTATE : 1;
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unsigned PCTR_RST_VAL : 16;
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} CTRL_bit;
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}; // 0x0
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/* PRU_CTRL_STS register bit field */
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union {
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volatile uint32_t STS;
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volatile struct {
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unsigned PCTR : 16;
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unsigned rsvd16 : 16;
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} STS_bit;
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}; // 0x4
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/* PRU_CTRL_WAKEUP_EN register bit field */
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union {
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volatile uint32_t WAKEUP_EN;
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volatile struct {
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unsigned BITWISE_ENS : 32;
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} WAKEUP_EN_bit;
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}; // 0x8
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/* PRU_CTRL_CYCLE register bit field */
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union {
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volatile uint32_t CYCLE;
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volatile struct {
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unsigned CYCLECOUNT : 32;
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} CYCLE_bit;
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}; // 0xC
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/* PRU_CTRL_STALL register bit field */
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union {
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volatile uint32_t STALL;
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volatile struct {
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unsigned STALLCOUNT : 32;
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} STALL_bit;
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}; // 0x10
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uint32_t rsvd14[3]; // 0x14 - 0x1C
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/* PRU_CTRL_CTBIR0 register bit field */
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union {
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volatile uint32_t CTBIR0;
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volatile struct {
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unsigned C24_BLK_IDX : 8;
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unsigned rsvd8 : 8;
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unsigned C25_BLK_IDX : 8;
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unsigned rsvd24 : 8;
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} CTBIR0_bit;
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}; // 0x20
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/* PRU_CTRL_CTBIR1 register bit field */
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union {
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volatile uint32_t CTBIR1;
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volatile struct {
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unsigned C26_BLK_IDX : 8;
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unsigned rsvd8 : 8;
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unsigned C27_BLK_IDX : 8;
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unsigned rsvd24 : 8;
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} CTBIR1_bit;
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}; // 0x24
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/* PRU_CTRL_CTPPR0 register bit field */
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union {
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volatile uint32_t CTPPR0;
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volatile struct {
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unsigned C28_BLK_POINTER : 16;
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unsigned C29_BLK_POINTER : 16;
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} CTPPR0_bit;
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}; // 0x28
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/* PRU_CTRL_CTPPR1 register bit field */
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union {
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volatile uint32_t CTPPR1;
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volatile struct {
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unsigned C30_BLK_POINTER : 16;
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unsigned C31_BLK_POINTER : 16;
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} CTPPR1_bit;
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}; // 0x2C
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} pruCtrl;
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/* Definition of control register structures. */
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#define PRU0_CTRL (*((volatile pruCtrl*)0x22000))
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#define PRU1_CTRL (*((volatile pruCtrl*)0x24000))
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#endif /* _PRU_CTRL_H_ */
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@ -0,0 +1,128 @@
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/*
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* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PRU_ECAP_H_
|
||||
#define _PRU_ECAP_H_
|
||||
|
||||
/* PRU_ECAP register set */
|
||||
typedef struct {
|
||||
|
||||
/* PRU_ECAP_TSCTR register bit field */
|
||||
union {
|
||||
volatile uint32_t TSCTR;
|
||||
|
||||
volatile struct {
|
||||
unsigned TSCTR : 32; //31:0
|
||||
} TSCTR_bit;
|
||||
}; // 0x0
|
||||
|
||||
/* PRU_ECAP_CTRPHS register bit field */
|
||||
union {
|
||||
volatile uint32_t CTRPHS;
|
||||
|
||||
volatile struct {
|
||||
unsigned CTRPHS : 32; //31:0
|
||||
} CTRPHS_bit;
|
||||
}; // 0x4
|
||||
|
||||
/* PRU_ECAP_CAP1 register bit field */
|
||||
union {
|
||||
volatile uint32_t CAP1;
|
||||
|
||||
volatile struct {
|
||||
unsigned CAP1 : 32; //31:0
|
||||
} CAP1_bit;
|
||||
}; // 0x8
|
||||
|
||||
/* PRU_ECAP_CAP2 register bit field */
|
||||
union {
|
||||
volatile uint32_t CAP2;
|
||||
|
||||
volatile struct {
|
||||
unsigned CAP2 : 32; //31:0
|
||||
} CAP2_bit;
|
||||
}; // 0xC
|
||||
|
||||
/* PRU_ECAP_CAP3 register bit field */
|
||||
union {
|
||||
volatile uint32_t CAP3;
|
||||
|
||||
volatile struct {
|
||||
unsigned CAP3 : 32; //31:0
|
||||
} CAP3_bit;
|
||||
}; // 0x10
|
||||
|
||||
/* PRU_ECAP_CAP4 register bit field */
|
||||
union {
|
||||
volatile uint32_t CAP4;
|
||||
|
||||
volatile struct {
|
||||
unsigned CAP4 : 32; //31:0
|
||||
} CAP4_bit;
|
||||
}; // 0x14
|
||||
|
||||
uint32_t rsvd118[4]; // 0x118 - 0x124
|
||||
|
||||
/* PRU_ECAP_ECCTL1 register bit field */
|
||||
volatile uint16_t ECCTL1; // 0x28
|
||||
|
||||
/* PRU_ECAP_ECCTL2 register bit field */
|
||||
volatile uint16_t ECCTL2; // 0x2A
|
||||
|
||||
/* PRU_ECAP_ECEINT register bit field */
|
||||
volatile uint16_t ECEINT; // 0x2C
|
||||
|
||||
/* PRU_ECAP_ECFLG register bit field */
|
||||
volatile uint16_t ECFLG; // 0x2E
|
||||
|
||||
/* PRU_ECAP_ECCLR register bit field */
|
||||
volatile uint16_t ECCLR; // 0x30
|
||||
|
||||
/* PRU_ECAP_ECFRC register bit field */
|
||||
volatile uint16_t ECFRC; // 0x32
|
||||
|
||||
uint32_t rsvd34[10]; // 0x34 - 0x58
|
||||
|
||||
/* PRU_ECAP_REVID register bit field */
|
||||
union {
|
||||
volatile uint32_t REVID;
|
||||
|
||||
volatile struct {
|
||||
unsigned REV : 32; //31:0
|
||||
} REVID_bit;
|
||||
}; // 0x5C
|
||||
} pruEcap;
|
||||
|
||||
volatile __far pruEcap CT_ECAP __attribute__((cregister("PRU_ECAP", near), peripheral));
|
||||
|
||||
#endif /* _PRU_ECAP_H_ */
|
|
@ -0,0 +1,261 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PRU_IEP_H_
|
||||
#define _PRU_IEP_H_
|
||||
|
||||
/* PRU IEP register set */
|
||||
typedef struct {
|
||||
|
||||
/* PRU_IEP_TMR_GLB_CFG register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_GLB_CFG;
|
||||
|
||||
volatile struct {
|
||||
unsigned CNT_EN : 1; // 0
|
||||
unsigned rsvd1 : 3; // 3:1
|
||||
unsigned DEFAULT_INC : 4; // 7:4
|
||||
unsigned CMP_INC : 12; // 19:8
|
||||
unsigned rsvd12 : 12; // 31:20
|
||||
} TMR_GLB_CFG_bit;
|
||||
}; // 0x0
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_GLB_STS register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_GLB_STS;
|
||||
|
||||
volatile struct {
|
||||
unsigned CNT_OVF : 1; // 0
|
||||
unsigned rsvd1 : 31; // 31:1
|
||||
} TMR_GLB_STS_bit;
|
||||
}; // 0x4
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_COMPEN register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_COMPEN;
|
||||
|
||||
volatile struct {
|
||||
unsigned COMPEN_CNT : 24; // 23:0
|
||||
unsigned rsvd24 : 8; // 31:24
|
||||
} TMR_COMPEN_bit;
|
||||
}; // 0x8
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CNT register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CNT;
|
||||
|
||||
volatile struct {
|
||||
unsigned COUNT : 32; // 31:0
|
||||
} TMR_CNT_bit;
|
||||
}; // 0xC
|
||||
|
||||
|
||||
uint32_t rsvd10[12]; // 0x10 - 0x3C
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CMP_CFG register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP_CFG;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP0_RST_CNT_EN : 1; // 0
|
||||
unsigned CMP_EN : 8; // 8:1
|
||||
unsigned rsvd9 : 23; // 31:9
|
||||
} TMR_CMP_CFG_bit;
|
||||
}; // 0x40
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CMP_STS register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP_STS;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP_HIT : 8; // 7:0
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} TMR_CMP_STS_bit;
|
||||
}; // 0x44
|
||||
|
||||
/* PRU_IEP_TMR_CMP0 register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP0;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP0 : 32; // 31:0
|
||||
} TMR_CMP0_bit;
|
||||
}; // 0x48
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CMP1 register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP1;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP1 : 32; // 31:0
|
||||
} TMR_CMP1_bit;
|
||||
}; // 0x4C
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CMP2 register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP2;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP2 : 32; // 31:0
|
||||
} TMR_CMP2_bit;
|
||||
}; // 0x50
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CMP3 register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP3;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP3 : 32; // 31:0
|
||||
} TMR_CMP3_bit;
|
||||
}; // 0x54
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CMP4 register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP4;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP4 : 32; // 31:0
|
||||
} TMR_CMP4_bit;
|
||||
}; // 0x58
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CMP5 register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP5;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP5 : 32; // 31:0
|
||||
} TMR_CMP5_bit;
|
||||
}; // 0x5C
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CMP6 register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP6;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP6 : 32; // 31:0
|
||||
} TMR_CMP6_bit;
|
||||
}; // 0x60
|
||||
|
||||
|
||||
/* PRU_IEP_TMR_CMP7 register bit field */
|
||||
union {
|
||||
volatile uint32_t TMR_CMP7;
|
||||
|
||||
volatile struct {
|
||||
unsigned CMP7 : 32; // 31:0
|
||||
} TMR_CMP7_bit;
|
||||
}; // 0x64
|
||||
|
||||
uint32_t rsvd68[166]; // 0x68 - 0x2FF
|
||||
|
||||
/* PRU_IEP_DIGIO_CTRL register bit field */
|
||||
union {
|
||||
volatile uint32_t DIGIO_CTRL;
|
||||
|
||||
volatile struct {
|
||||
unsigned RESERVED0 : 4; // 3:0
|
||||
unsigned IN_MODE : 1; // 4
|
||||
unsigned RESERVED5 : 27; // 31:5
|
||||
} DIGIO_CTRL_bit;
|
||||
}; // 0x300
|
||||
|
||||
uint32_t rsvd304[1]; // 0x304
|
||||
|
||||
/* PRU_IEP_DIGIO_DATA_IN register bit field */
|
||||
union {
|
||||
volatile uint32_t DIGIO_DATA_IN;
|
||||
|
||||
volatile struct {
|
||||
unsigned DATA_IN : 32; // 31:0
|
||||
} DIGIO_DATA_IN_bit;
|
||||
}; // 0x308
|
||||
|
||||
/* PRU_IEP_DIGIO_DATA_IN_RAW register bit field */
|
||||
union {
|
||||
volatile uint32_t DIGIO_DATA_IN_RAW;
|
||||
|
||||
volatile struct {
|
||||
unsigned DATA_IN_RAW : 32; // 31:0
|
||||
} DIGIO_DATA_IN_RAW_bit;
|
||||
}; // 0x30C
|
||||
|
||||
/* PRU_IEP_DIGIO_DATA_OUT register bit field */
|
||||
union {
|
||||
volatile uint32_t DIGIO_DATA_OUT;
|
||||
|
||||
volatile struct {
|
||||
unsigned DATA_OUT : 32; // 31:0
|
||||
} DIGIO_DATA_OUT_bit;
|
||||
}; // 0x310
|
||||
|
||||
/* PRU_IEP_DIGIO_DATA_OUT_EN register bit field */
|
||||
union {
|
||||
volatile uint32_t DIGIO_DATA_OUT_EN;
|
||||
|
||||
volatile struct {
|
||||
unsigned DATA_OUT_EN : 32; // 31:0
|
||||
} DIGIO_DATA_OUT_EN_bit;
|
||||
}; // 0x314
|
||||
|
||||
/* PRU_IEP_DIGIO_EXP register bit field */
|
||||
union {
|
||||
volatile uint32_t DIGIO_EXP;
|
||||
|
||||
volatile struct {
|
||||
unsigned SW_DATA_OUT_UPDATE : 1; // 0
|
||||
unsigned OUTVALID_OVR_EN : 1; // 1
|
||||
unsigned RESERVED2 : 30; // 31:2
|
||||
} DIGIO_EXP_bit;
|
||||
}; // 0x318
|
||||
|
||||
} pruIep;
|
||||
|
||||
#ifdef __GNUC__
|
||||
static volatile pruIep *__CT_IEP = (void *)0x0002e000;
|
||||
#define CT_IEP (*__CT_IEP)
|
||||
#else
|
||||
volatile __far pruIep CT_IEP __attribute__((cregister("PRU_IEP", far), peripheral));
|
||||
#endif
|
||||
|
||||
#endif /* _PRU_IEP_H_ */
|
|
@ -0,0 +1,912 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PRU_INTC_H_
|
||||
#define _PRU_INTC_H_
|
||||
|
||||
/* PRU INTC register set */
|
||||
typedef struct {
|
||||
|
||||
/* PRU_INTC_REVID register bit field */
|
||||
union {
|
||||
volatile uint32_t REVID;
|
||||
|
||||
volatile struct {
|
||||
unsigned REV_MINOR : 6; // 5:0
|
||||
unsigned REV_CUSTOM : 2; // 7:6
|
||||
unsigned REV_MAJOR : 3; // 10:8
|
||||
unsigned REV_RTL : 5; // 15:11
|
||||
unsigned REV_MODULE : 12; // 27:16
|
||||
unsigned rsvd28 : 2; // 29:28
|
||||
unsigned REV_SCHEME : 2; // 31:30
|
||||
} REVID_bit;
|
||||
}; // 0x0
|
||||
|
||||
|
||||
/* PRU_INTC_CR register bit field */
|
||||
union {
|
||||
volatile uint32_t CR;
|
||||
|
||||
volatile struct {
|
||||
unsigned rsvd0 : 2; // 1:0
|
||||
unsigned NEST_MODE : 2; // 3:2
|
||||
unsigned rsvd4 : 28; // 31:4
|
||||
} CR_bit;
|
||||
}; // 0x4
|
||||
|
||||
|
||||
uint32_t rsvd8[2]; // 0x8 - 0xC
|
||||
|
||||
|
||||
/* PRU_INTC_GER register bit field */
|
||||
union {
|
||||
volatile uint32_t GER;
|
||||
|
||||
volatile struct {
|
||||
unsigned EN_HINT_ANY : 1; // 0
|
||||
unsigned rsvd1 : 31; // 31:1
|
||||
} GER_bit;
|
||||
}; // 0x10
|
||||
|
||||
|
||||
uint32_t rsvd14[2]; // 0x14 - 0x18
|
||||
|
||||
|
||||
/* PRU_INTC_GNLR register bit field */
|
||||
union {
|
||||
volatile uint32_t GNLR;
|
||||
|
||||
volatile struct {
|
||||
unsigned GLB_NEST_LEVEL : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} GNLR_bit;
|
||||
}; // 0x1C
|
||||
|
||||
|
||||
/* PRU_INTC_SISR register bit field */
|
||||
union {
|
||||
volatile uint32_t SISR;
|
||||
|
||||
volatile struct {
|
||||
unsigned STS_SET_IDX : 10; // 9:0
|
||||
unsigned rsvd10 : 22; // 31:10
|
||||
} SISR_bit;
|
||||
}; // 0x20
|
||||
|
||||
|
||||
/* PRU_INTC_SICR register bit field */
|
||||
union {
|
||||
volatile uint32_t SICR;
|
||||
|
||||
volatile struct {
|
||||
unsigned STS_CLR_IDX : 10; // 9:0
|
||||
unsigned rsvd10 : 22; // 31:10
|
||||
} SICR_bit;
|
||||
}; // 0x24
|
||||
|
||||
|
||||
/* PRU_INTC_EISR register bit field */
|
||||
union {
|
||||
volatile uint32_t EISR;
|
||||
|
||||
volatile struct {
|
||||
unsigned EN_SET_IDX : 10; // 9:0
|
||||
unsigned rsvd10 : 22; // 31:10
|
||||
} EISR_bit;
|
||||
}; // 0x28
|
||||
|
||||
|
||||
/* PRU_INTC_EICR register bit field */
|
||||
union {
|
||||
volatile uint32_t EICR;
|
||||
|
||||
volatile struct {
|
||||
unsigned EN_CLR_IDX : 10; // 9:0
|
||||
unsigned rsvd10 : 22; // 31:10
|
||||
} EICR_bit;
|
||||
}; // 0x2C
|
||||
|
||||
|
||||
uint32_t rsvd30; // 0x30
|
||||
|
||||
|
||||
/* PRU_INTC_HIEISR register bit field */
|
||||
union {
|
||||
volatile uint32_t HIEISR;
|
||||
|
||||
volatile struct {
|
||||
unsigned HINT_EN_SET_IDX : 4; // 3:0
|
||||
unsigned rsvd4 : 28; // 31:4
|
||||
} HIEISR_bit;
|
||||
}; // 0x34
|
||||
|
||||
|
||||
/* PRU_INTC_HIDISR register bit field */
|
||||
union {
|
||||
volatile uint32_t HIDISR;
|
||||
|
||||
volatile struct {
|
||||
unsigned HINT_EN_CLR_IDX : 4; // 3:0
|
||||
unsigned rsvd4 : 28; // 31:4
|
||||
} HIDISR_bit;
|
||||
}; // 0x38
|
||||
|
||||
|
||||
uint32_t rsvd3C[17]; // 0x3C - 0x7C
|
||||
|
||||
|
||||
/* PRU_INTC_GPIR register bit field */
|
||||
union {
|
||||
volatile uint32_t GPIR;
|
||||
|
||||
volatile struct {
|
||||
unsigned GLB_PRI_INTR : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned GLB_NONE : 1; // 31
|
||||
} GPIR_bit;
|
||||
}; // 0x80
|
||||
|
||||
|
||||
uint32_t rsvd84[95]; // 0x84 - 0x1FC
|
||||
|
||||
|
||||
/* PRU_INTC_SRSR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t SRSR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned RAW_STS_31_0 : 32; // 31:0
|
||||
} SRSR0_bit;
|
||||
}; // 0x200
|
||||
|
||||
|
||||
/* PRU_INTC_SRSR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t SRSR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned RAW_STS_63_32 : 32; // 31:0
|
||||
} SRSR1_bit;
|
||||
}; // 0x204
|
||||
|
||||
|
||||
uint32_t rsvd208[30]; // 0x208 - 0x27C
|
||||
|
||||
|
||||
/* PRU_INTC_SECR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t SECR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned ENA_STS_31_0 : 32; // 31:0
|
||||
} SECR0_bit;
|
||||
}; // 0x280
|
||||
|
||||
|
||||
/* PRU_INTC_SECR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t SECR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned ENA_STS_63_32 : 32; // 31:0
|
||||
} SECR1_bit;
|
||||
}; // 0x284
|
||||
|
||||
|
||||
uint32_t rsvd288[30]; // 0x288 - 0x2FC
|
||||
|
||||
|
||||
/* PRU_INTC_ESR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t ESR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned EN_SET_31_0 : 32; // 31:0
|
||||
} ESR0_bit;
|
||||
}; // 0x300
|
||||
|
||||
|
||||
/* PRU_INTC_ESR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t ESR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned EN_SET_63_32 : 32; // 31:0
|
||||
} ESR1_bit;
|
||||
}; // 0x304
|
||||
|
||||
|
||||
uint32_t rsvd308[30]; // 0x308 - 0x37C
|
||||
|
||||
|
||||
/* PRU_INTC_ECR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t ECR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned EN_CLR_31_0 : 32; // 31:0
|
||||
} ECR0_bit;
|
||||
}; // 0x380
|
||||
|
||||
|
||||
/* PRU_INTC_ECR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t ECR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned EN_CLR_63_32 : 32; // 31:0
|
||||
} ECR1_bit;
|
||||
}; // 0x384
|
||||
|
||||
|
||||
uint32_t rsvd388[30]; // 0x388 - 0x3FC
|
||||
|
||||
|
||||
/* PRU_INTC_CMR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_0 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_1 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_2 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_3 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR0_bit;
|
||||
}; // 0x400
|
||||
|
||||
|
||||
/* PRU_INTC_CMR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_4 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_5 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_6 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_7 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR1_bit;
|
||||
}; // 0x404
|
||||
|
||||
|
||||
/* PRU_INTC_CMR2 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR2;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_8 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_9 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_10 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_11 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR2_bit;
|
||||
}; // 0x408
|
||||
|
||||
|
||||
/* PRU_INTC_CMR3 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR3;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_12 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_13 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_14 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_15 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR3_bit;
|
||||
}; // 0x40C
|
||||
|
||||
|
||||
/* PRU_INTC_CMR4 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR4;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_16 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_17 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_18 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_19 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR4_bit;
|
||||
}; // 0x410
|
||||
|
||||
|
||||
/* PRU_INTC_CMR5 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR5;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_20 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_21 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_22 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_23 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR5_bit;
|
||||
}; // 0x414
|
||||
|
||||
|
||||
/* PRU_INTC_CMR6 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR6;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_24 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_25 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_26 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_27 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR6_bit;
|
||||
}; // 0x418
|
||||
|
||||
|
||||
/* PRU_INTC_CMR7 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR7;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_28 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_29 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_30 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_31 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR7_bit;
|
||||
}; // 0x41C
|
||||
|
||||
|
||||
/* PRU_INTC_CMR8 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR8;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_32 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_33 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_34 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_35 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR8_bit;
|
||||
}; // 0x420
|
||||
|
||||
|
||||
/* PRU_INTC_CMR9 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR9;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_36 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_37 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_38 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_39 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR9_bit;
|
||||
}; // 0x424
|
||||
|
||||
|
||||
/* PRU_INTC_CMR10 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR10;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_40 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_41 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_42 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_43 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR10_bit;
|
||||
}; // 0x428
|
||||
|
||||
|
||||
/* PRU_INTC_CMR11 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR11;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_44 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_45 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_46 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_47 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR11_bit;
|
||||
}; // 0x42C
|
||||
|
||||
|
||||
/* PRU_INTC_CMR12 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR12;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_48 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_49 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_50 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_51 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR12_bit;
|
||||
}; // 0x430
|
||||
|
||||
|
||||
/* PRU_INTC_CMR13 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR13;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_52 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_53 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_54 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_55 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR13_bit;
|
||||
}; // 0x434
|
||||
|
||||
|
||||
/* PRU_INTC_CMR14 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR14;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_56 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_57 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_58 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_59 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR14_bit;
|
||||
}; // 0x438
|
||||
|
||||
|
||||
/* PRU_INTC_CMR15 register bit field */
|
||||
union {
|
||||
volatile uint32_t CMR15;
|
||||
|
||||
volatile struct {
|
||||
unsigned CH_MAP_60 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned CH_MAP_61 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned CH_MAP_62 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned CH_MAP_63 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} CMR15_bit;
|
||||
}; // 0x43C
|
||||
|
||||
|
||||
uint32_t rsvd440[240]; // 0x440 - 0x7FC
|
||||
|
||||
|
||||
/* PRU_INTC_HMR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t HMR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned HINT_MAP_0 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned HINT_MAP_1 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned HINT_MAP_2 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned HINT_MAP_3 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} HMR0_bit;
|
||||
}; // 0x800
|
||||
|
||||
|
||||
/* PRU_INTC_HMR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t HMR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned HINT_MAP_4 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned HINT_MAP_5 : 4; // 11:8
|
||||
unsigned rsvd12 : 4; // 15:12
|
||||
unsigned HINT_MAP_6 : 4; // 19:16
|
||||
unsigned rsvd20 : 4; // 23:20
|
||||
unsigned HINT_MAP_7 : 4; // 27:24
|
||||
unsigned rsvd28 : 4; // 31:28
|
||||
} HMR1_bit;
|
||||
}; // 0x804
|
||||
|
||||
|
||||
/* PRU_INTC_HMR2 register bit field */
|
||||
union {
|
||||
volatile uint32_t HMR2;
|
||||
|
||||
volatile struct {
|
||||
unsigned HINT_MAP_8 : 4; // 3:0
|
||||
unsigned rsvd4 : 4; // 7:4
|
||||
unsigned HINT_MAP_9 : 4; // 11:8
|
||||
unsigned rsvd12 : 20; // 31:12
|
||||
} HMR2_bit;
|
||||
}; // 0x808
|
||||
|
||||
|
||||
uint32_t rsvd80C[61]; // 0x80C - 0x8FC
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_0 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_0 : 1; // 31
|
||||
} HIPIR0_bit;
|
||||
}; // 0x900
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_1 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_1 : 1; // 31
|
||||
} HIPIR1_bit;
|
||||
}; // 0x904
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR2 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR2;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_2 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_2 : 1; // 31
|
||||
} HIPIR2_bit;
|
||||
}; // 0x908
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR3 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR3;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_3 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_3 : 1; // 31
|
||||
} HIPIR3_bit;
|
||||
}; // 0x90C
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR4 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR4;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_4 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_4 : 1; // 31
|
||||
} HIPIR4_bit;
|
||||
}; // 0x910
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR5 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR5;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_5 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_5 : 1; // 31
|
||||
} HIPIR5_bit;
|
||||
}; // 0x914
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR6 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR6;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_6 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_6 : 1; // 31
|
||||
} HIPIR6_bit;
|
||||
}; // 0x918
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR7 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR7;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_7 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_7 : 1; // 31
|
||||
} HIPIR7_bit;
|
||||
}; // 0x91C
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR8 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR8;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_8 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_8 : 1; // 31
|
||||
} HIPIR8_bit;
|
||||
}; // 0x920
|
||||
|
||||
|
||||
/* PRU_INTC_HIPIR9 register bit field */
|
||||
union {
|
||||
volatile uint32_t HIPIR9;
|
||||
|
||||
volatile struct {
|
||||
unsigned PRI_HINT_9 : 10; // 9:0
|
||||
unsigned rsvd10 : 21; // 30:10
|
||||
unsigned NONE_HINT_9 : 1; // 31
|
||||
} HIPIR9_bit;
|
||||
}; // 0x924
|
||||
|
||||
|
||||
uint32_t rsvd928[246]; // 0x928 - 0xCFC
|
||||
|
||||
|
||||
/* PRU_INTC_SIPR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t SIPR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned POLARITY_31_0 : 32; // 31:0
|
||||
} SIPR0_bit;
|
||||
}; // 0xD00
|
||||
|
||||
|
||||
/* PRU_INTC_SIPR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t SIPR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned POLARITY_63_32 : 32; // 31:0
|
||||
} SIPR1_bit;
|
||||
}; // 0xD04
|
||||
|
||||
|
||||
uint32_t rsvdD08[30]; // 0xD08 - 0xD7C
|
||||
|
||||
|
||||
/* PRU_INTC_SITR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t SITR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned TYPE_31_0 : 32; // 31:0
|
||||
} SITR0_bit;
|
||||
}; // 0xD80
|
||||
|
||||
|
||||
/* PRU_INTC_SITR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t SITR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned TYPE_63_32 : 32; // 31:0
|
||||
} SITR1_bit;
|
||||
}; // 0xD84
|
||||
|
||||
|
||||
uint32_t rsvdD84[222]; // 0xD88 - 0x10FC
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR0 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR0;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_0 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR0_bit;
|
||||
}; // 0x1100
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR1 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR1;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_1 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR1_bit;
|
||||
}; // 0x1104
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR2 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR2;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_2 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR2_bit;
|
||||
}; // 0x1108
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR3 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR3;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_3 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR3_bit;
|
||||
}; // 0x110C
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR4 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR4;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_4 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR4_bit;
|
||||
}; // 0x1110
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR5 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR5;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_5 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR5_bit;
|
||||
}; // 0x1114
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR6 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR6;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_6 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR6_bit;
|
||||
}; // 0x1118
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR7 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR7;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_7 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR7_bit;
|
||||
}; // 0x111C
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR8 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR8;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_8 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR8_bit;
|
||||
}; // 0x1120
|
||||
|
||||
|
||||
/* PRU_INTC_HINLR9 register bit field */
|
||||
union {
|
||||
volatile uint32_t HINLR9;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEST_HINT_9 : 9; // 8:0
|
||||
unsigned rsvd9 : 22; // 30:9
|
||||
unsigned AUTO_OVERRIDE : 1; // 31
|
||||
} HINLR9_bit;
|
||||
}; // 0x1124
|
||||
|
||||
|
||||
uint32_t rsvd1128[246]; // 0x1128 - 0x14FC
|
||||
|
||||
|
||||
/* PRU_INTC_HIER register bit field */
|
||||
union {
|
||||
volatile uint32_t HIER;
|
||||
|
||||
volatile struct {
|
||||
unsigned EN_HINT : 10; // 9:0
|
||||
unsigned rsvd9 : 22; // 31:10
|
||||
} HIER_bit;
|
||||
}; // 0x1500
|
||||
|
||||
} pruIntc;
|
||||
|
||||
#ifdef __GNUC__
|
||||
static volatile pruIntc *__CT_INTC = (void *)0x00020000;
|
||||
#define CT_INTC (*__CT_INTC)
|
||||
#else
|
||||
volatile __far pruIntc CT_INTC __attribute__((cregister("PRU_INTC", far), peripheral));
|
||||
#endif
|
||||
|
||||
#endif /* _PRU_INTC_H_ */
|
|
@ -0,0 +1,285 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PRU_UART_H_
|
||||
#define _PRU_UART_H_
|
||||
|
||||
/* UART Register set */
|
||||
typedef struct {
|
||||
|
||||
/*
|
||||
* RBR and THR register pair
|
||||
* This is a unique register pair in that RBR and THR
|
||||
* share the same address. RBR is read-only while THR is
|
||||
* write-only.
|
||||
*
|
||||
* Additionally, RBR and THR share an address with DLL. To
|
||||
* read/write RBR/THR write 0 to the DLAB bit in the LCR
|
||||
* register. To modify DLL write a 1.
|
||||
*
|
||||
* DLL also has a dedicated
|
||||
* address which does not require toggling the DLAB bit.
|
||||
*/
|
||||
union {
|
||||
/* PRU_UART_RBR register bit field */
|
||||
union {
|
||||
volatile uint32_t RBR;
|
||||
|
||||
volatile struct {
|
||||
unsigned DATA : 8; // 7:0
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} RBR_bit;
|
||||
};
|
||||
|
||||
/* PRU_UART_THR register bit field */
|
||||
union {
|
||||
volatile uint32_t THR;
|
||||
|
||||
volatile struct {
|
||||
unsigned DATA : 8; // 7:0
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} THR_bit;
|
||||
};
|
||||
}; // 0x0
|
||||
|
||||
|
||||
/* PRU_UART_IER register bit field */
|
||||
/*
|
||||
* IER shares an address with DLH. To modify IER write 0
|
||||
* to the DLAB bit in the LCR register. To modify DLH write a 1.
|
||||
*
|
||||
* DLH also has a dedicated address which does not require
|
||||
* toggling the DLAB bit.
|
||||
*/
|
||||
union {
|
||||
volatile uint32_t IER;
|
||||
|
||||
volatile struct {
|
||||
unsigned ERBI : 1; // 0
|
||||
unsigned ETBEI : 1; // 1
|
||||
unsigned ELSI : 1; // 2
|
||||
unsigned EDSSI : 1; // 3
|
||||
unsigned rsvd4 : 28; // 31:4
|
||||
} IER_bit;
|
||||
}; // 0x4
|
||||
|
||||
|
||||
/*
|
||||
* IIR and FCR register pair
|
||||
* This is a unique register pair in that IIR and FCR
|
||||
* share the same address. IIR is read-only while FCR is
|
||||
* write-only.
|
||||
*/
|
||||
union {
|
||||
/* PRU_UART_IIR register bit field */
|
||||
union {
|
||||
volatile uint32_t IIR;
|
||||
|
||||
volatile struct {
|
||||
unsigned IPEND : 1; // 0
|
||||
unsigned INTID : 3; // 3:1
|
||||
unsigned rsvd4 : 2; // 5:4
|
||||
unsigned FIFOEN : 2; // 7:6
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} IIR_bit;
|
||||
};
|
||||
|
||||
/* PRU_UART_FCR register bit field */
|
||||
union {
|
||||
volatile uint32_t FCR;
|
||||
|
||||
volatile struct {
|
||||
unsigned FIFOEN : 1; // 0
|
||||
unsigned RXCLR : 1; // 1
|
||||
unsigned TXCLR : 1; // 2
|
||||
unsigned DMAMODE1 : 1; // 3
|
||||
unsigned rsvd4 : 2; // 5:4
|
||||
unsigned RXFIFTL : 2; // 7:6
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} FCR_bit;
|
||||
};
|
||||
}; // 0x8
|
||||
|
||||
|
||||
/* PRU_UART_LCR register bit field */
|
||||
union {
|
||||
volatile uint32_t LCR;
|
||||
|
||||
volatile struct {
|
||||
unsigned WLS : 2; // 1:0
|
||||
unsigned STB : 1; // 2
|
||||
unsigned PEN : 1; // 3
|
||||
unsigned EPS : 1; // 4
|
||||
unsigned SP : 1; // 5
|
||||
unsigned BC : 1; // 6
|
||||
unsigned DLAB : 1; // 7
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} LCR_bit;
|
||||
}; // 0xC
|
||||
|
||||
|
||||
/* PRU_UART_MCR register bit field */
|
||||
union {
|
||||
volatile uint32_t MCR;
|
||||
|
||||
volatile struct {
|
||||
unsigned rsvd0 : 1; // 0
|
||||
unsigned RTS : 1; // 1
|
||||
unsigned OUT1 : 1; // 2
|
||||
unsigned OUT2 : 1; // 3
|
||||
unsigned LOOP : 1; // 4
|
||||
unsigned AFE : 1; // 5
|
||||
unsigned rsvd8 : 26; // 31:6
|
||||
} MCR_bit;
|
||||
}; // 0x10
|
||||
|
||||
|
||||
/* PRU_UART_LSR register bit field */
|
||||
union {
|
||||
volatile uint32_t LSR;
|
||||
|
||||
volatile struct {
|
||||
unsigned DR : 1; // 0
|
||||
unsigned OE : 1; // 1
|
||||
unsigned PE : 1; // 2
|
||||
unsigned FE : 1; // 3
|
||||
unsigned BI : 1; // 4
|
||||
unsigned THRE : 1; // 5
|
||||
unsigned TEMT : 1; // 6
|
||||
unsigned RXFIFOE : 1; // 7
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} LSR_bit;
|
||||
}; // 0x14
|
||||
|
||||
|
||||
/* PRU_UART_MSR register bit field */
|
||||
union {
|
||||
volatile uint32_t MSR;
|
||||
|
||||
volatile struct {
|
||||
unsigned DCTS : 1; // 0
|
||||
unsigned DDSR : 1; // 1
|
||||
unsigned TERI : 1; // 2
|
||||
unsigned DCD : 1; // 3
|
||||
unsigned CTS : 1; // 4
|
||||
unsigned DSR : 1; // 5
|
||||
unsigned RI : 1; // 6
|
||||
unsigned CD : 1; // 7
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} MSR_bit;
|
||||
}; // 0x18
|
||||
|
||||
|
||||
/* PRU_UART_SCR register bit field */
|
||||
union {
|
||||
volatile uint32_t SCR;
|
||||
|
||||
volatile struct {
|
||||
unsigned SCR : 8; // 7:0
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} SCR_bit;
|
||||
}; // 0x1C
|
||||
|
||||
|
||||
/* PRU_UART_DLL register bit field */
|
||||
union {
|
||||
volatile uint32_t DLL;
|
||||
|
||||
volatile struct {
|
||||
unsigned DLL : 8; // 7:0
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} DLL_bit;
|
||||
}; // 0x20
|
||||
|
||||
|
||||
/* PRU_UART_DLH register bit field */
|
||||
union {
|
||||
volatile uint32_t DLH;
|
||||
|
||||
volatile struct {
|
||||
unsigned DLH : 8; // 7:0
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} DLH_bit;
|
||||
}; // 0x24
|
||||
|
||||
|
||||
/* PRU_UART_REVID1 register bit field */
|
||||
union {
|
||||
volatile uint32_t REVID1;
|
||||
|
||||
volatile struct {
|
||||
unsigned REVID1 : 32; // 31:0
|
||||
} REVID1_bit;
|
||||
}; // 0x28
|
||||
|
||||
|
||||
/* PRU_UART_REVID2 register bit field */
|
||||
union {
|
||||
volatile uint32_t REVID2;
|
||||
|
||||
volatile struct {
|
||||
unsigned REVID2 : 8; // 7:0
|
||||
unsigned rsvd8 : 24; // 31:8
|
||||
} REVID2_bit;
|
||||
}; // 0x2C
|
||||
|
||||
|
||||
/* PRU_UART_PWREMU_MGMT register bit field */
|
||||
union {
|
||||
volatile uint32_t PWREMU_MGMT;
|
||||
|
||||
volatile struct {
|
||||
unsigned FREE : 1; // 0
|
||||
unsigned rsvd1 : 12; // 12:1
|
||||
unsigned URRST : 1; // 13
|
||||
unsigned UTRST : 1; // 14
|
||||
unsigned rsvd15 : 17; // 31:15
|
||||
} PWREMU_MGMT_bit;
|
||||
}; // 0x30
|
||||
|
||||
|
||||
/* PRU_UART_MDR register bit field */
|
||||
union {
|
||||
volatile uint32_t MDR;
|
||||
|
||||
volatile struct {
|
||||
unsigned OSM_SEL : 1; // 0
|
||||
unsigned rsvd1 : 31; // 31:1
|
||||
} MDR_bit;
|
||||
}; // 0x34
|
||||
|
||||
} pruUart;
|
||||
|
||||
volatile __far pruUart CT_UART __attribute__((cregister("PRU_UART", near), peripheral));
|
||||
|
||||
#endif /* _PRU_UART_H_ */
|
|
@ -0,0 +1,210 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _SYS_MAILBOX_H_
|
||||
#define _SYS_MAILBOX_H_
|
||||
|
||||
/* SYS_MAILBOX register set */
|
||||
typedef struct {
|
||||
|
||||
/* SYS_MAILBOX_REVISION register bit field */
|
||||
union {
|
||||
volatile uint32_t REVISION;
|
||||
|
||||
volatile struct {
|
||||
unsigned MINOR : 6; //5:0
|
||||
unsigned CUSTOM : 2; //7:6
|
||||
unsigned MAJOR : 3; //10:8
|
||||
unsigned RTL : 5; //15:11
|
||||
unsigned FUNC : 12; //27:16
|
||||
unsigned rsvd28 : 2; //29:28
|
||||
unsigned SCHEME : 2; //31:30
|
||||
} REVISION_bit;
|
||||
}; // 0x0
|
||||
|
||||
uint32_t rsvd4[3]; // 0x4 - 0xC
|
||||
|
||||
/* SYS_MAILBOX_SYSCONFIG register bit field */
|
||||
union {
|
||||
volatile uint32_t SYSCONFIG;
|
||||
|
||||
volatile struct {
|
||||
unsigned SOFTRESET : 1; //0
|
||||
unsigned rsvd : 1; //1
|
||||
unsigned SLIDLEMODE : 2; //3:2
|
||||
unsigned rsvd1 : 28; //31:4
|
||||
} SYSCONFIG_bit;
|
||||
}; // 0x10
|
||||
|
||||
uint32_t rsvd14[11]; // 0x14 - 0x3C
|
||||
|
||||
/* SYS_MAILBOX_MESSAGE register bit fields */
|
||||
union {
|
||||
volatile uint32_t MESSAGE[8];
|
||||
|
||||
volatile struct {
|
||||
unsigned MESSAGE : 32; //31:0
|
||||
} MESSAGE_bit[8];
|
||||
}; // 0x40-0x5C
|
||||
|
||||
uint32_t rsvd60[8]; // 0x60 - 0x7C
|
||||
|
||||
/* SYS_MAILBOX_FIFOSTATUS register bit fields */
|
||||
union {
|
||||
volatile uint32_t FIFOSTATUS[8];
|
||||
|
||||
volatile struct {
|
||||
unsigned FIFOFULL : 1; //0
|
||||
unsigned rsvd : 31; //31:1
|
||||
} FIFOSTATUS_bit[8];
|
||||
}; // 0x80-0x9C
|
||||
|
||||
uint32_t rsvdA0[8]; // 0xA0 - 0xBC
|
||||
|
||||
/* SYS_MAILBOX_MSGSTATUS register bit fields */
|
||||
union {
|
||||
volatile uint32_t MSGSTATUS[8];
|
||||
|
||||
volatile struct {
|
||||
unsigned NBOFMSG : 3; //2:0
|
||||
unsigned rsvd : 29; //31:3
|
||||
} MSGSTATUS_bit[8];
|
||||
}; // 0xC0-DC
|
||||
|
||||
uint32_t rsvdE0[8]; // 0xE0 - 0xFC
|
||||
|
||||
volatile struct {
|
||||
union {
|
||||
volatile uint32_t STATUS_RAW;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEWMSGSTATUSMB0 : 1; //0
|
||||
unsigned NOTFULLSTATUSMB0 : 1; //1
|
||||
unsigned NEWMSGSTATUSMB1 : 1; //2
|
||||
unsigned NOTFULLSTATUSMB1 : 1; //3
|
||||
unsigned NEWMSGSTATUSMB2 : 1; //4
|
||||
unsigned NOTFULLSTATUSMB2 : 1; //5
|
||||
unsigned NEWMSGSTATUSMB3 : 1; //6
|
||||
unsigned NOTFULLSTATUSMB3 : 1; //7
|
||||
unsigned NEWMSGSTATUSMB4 : 1; //8
|
||||
unsigned NOTFULLSTATUSMB4 : 1; //9
|
||||
unsigned NEWMSGSTATUSMB5 : 1; //10
|
||||
unsigned NOTFULLSTATUSMB5 : 1; //11
|
||||
unsigned NEWMSGSTATUSMB6 : 1; //12
|
||||
unsigned NOTFULLSTATUSMB6 : 1; //13
|
||||
unsigned NEWMSGSTATUSMB7 : 1; //14
|
||||
unsigned NOTFULLSTATUSMB7 : 1; //15
|
||||
unsigned rsvd : 16; //31:16
|
||||
} STATUS_RAW_bit;
|
||||
};
|
||||
union {
|
||||
volatile uint32_t STATUS_CLR;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEWMSGSTATUSMB0 : 1; //0
|
||||
unsigned NOTFULLSTATUSMB0 : 1; //1
|
||||
unsigned NEWMSGSTATUSMB1 : 1; //2
|
||||
unsigned NOTFULLSTATUSMB1 : 1; //3
|
||||
unsigned NEWMSGSTATUSMB2 : 1; //4
|
||||
unsigned NOTFULLSTATUSMB2 : 1; //5
|
||||
unsigned NEWMSGSTATUSMB3 : 1; //6
|
||||
unsigned NOTFULLSTATUSMB3 : 1; //7
|
||||
unsigned NEWMSGSTATUSMB4 : 1; //8
|
||||
unsigned NOTFULLSTATUSMB4 : 1; //9
|
||||
unsigned NEWMSGSTATUSMB5 : 1; //10
|
||||
unsigned NOTFULLSTATUSMB5 : 1; //11
|
||||
unsigned NEWMSGSTATUSMB6 : 1; //12
|
||||
unsigned NOTFULLSTATUSMB6 : 1; //13
|
||||
unsigned NEWMSGSTATUSMB7 : 1; //14
|
||||
unsigned NOTFULLSTATUSMB7 : 1; //15
|
||||
unsigned rsvd : 16; //31:16
|
||||
} STATUS_CLR_bit;
|
||||
};
|
||||
union {
|
||||
volatile uint32_t ENABLE_SET;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEWMSGSTATUSMB0 : 1; //0
|
||||
unsigned NOTFULLSTATUSMB0 : 1; //1
|
||||
unsigned NEWMSGSTATUSMB1 : 1; //2
|
||||
unsigned NOTFULLSTATUSMB1 : 1; //3
|
||||
unsigned NEWMSGSTATUSMB2 : 1; //4
|
||||
unsigned NOTFULLSTATUSMB2 : 1; //5
|
||||
unsigned NEWMSGSTATUSMB3 : 1; //6
|
||||
unsigned NOTFULLSTATUSMB3 : 1; //7
|
||||
unsigned NEWMSGSTATUSMB4 : 1; //8
|
||||
unsigned NOTFULLSTATUSMB4 : 1; //9
|
||||
unsigned NEWMSGSTATUSMB5 : 1; //10
|
||||
unsigned NOTFULLSTATUSMB5 : 1; //11
|
||||
unsigned NEWMSGSTATUSMB6 : 1; //12
|
||||
unsigned NOTFULLSTATUSMB6 : 1; //13
|
||||
unsigned NEWMSGSTATUSMB7 : 1; //14
|
||||
unsigned NOTFULLSTATUSMB7 : 1; //15
|
||||
unsigned rsvd : 16; //31:16
|
||||
} ENABLE_SET_bit;
|
||||
};
|
||||
union {
|
||||
volatile uint32_t ENABLE_CLR;
|
||||
|
||||
volatile struct {
|
||||
unsigned NEWMSGSTATUSMB0 : 1; //0
|
||||
unsigned NOTFULLSTATUSMB0 : 1; //1
|
||||
unsigned NEWMSGSTATUSMB1 : 1; //2
|
||||
unsigned NOTFULLSTATUSMB1 : 1; //3
|
||||
unsigned NEWMSGSTATUSMB2 : 1; //4
|
||||
unsigned NOTFULLSTATUSMB2 : 1; //5
|
||||
unsigned NEWMSGSTATUSMB3 : 1; //6
|
||||
unsigned NOTFULLSTATUSMB3 : 1; //7
|
||||
unsigned NEWMSGSTATUSMB4 : 1; //8
|
||||
unsigned NOTFULLSTATUSMB4 : 1; //9
|
||||
unsigned NEWMSGSTATUSMB5 : 1; //10
|
||||
unsigned NOTFULLSTATUSMB5 : 1; //11
|
||||
unsigned NEWMSGSTATUSMB6 : 1; //12
|
||||
unsigned NOTFULLSTATUSMB6 : 1; //13
|
||||
unsigned NEWMSGSTATUSMB7 : 1; //14
|
||||
unsigned NOTFULLSTATUSMB7 : 1; //15
|
||||
unsigned rsvd : 16; //31:16
|
||||
} ENABLE_CLR_bit;
|
||||
};
|
||||
} IRQ[4];
|
||||
|
||||
} sysMailbox;
|
||||
|
||||
#ifdef __GNUC__
|
||||
static volatile sysMailbox *__CT_MBX = (void *)0x480C8000;
|
||||
#define CT_MBX (*__CT_MBX)
|
||||
#else
|
||||
volatile __far sysMailbox CT_MBX __attribute__((cregister("MBX0", far), peripheral));
|
||||
#endif
|
||||
|
||||
#endif /* _SYS_MAILBOX_H_ */
|
|
@ -0,0 +1,446 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _SYS_PWMSS_H_
|
||||
#define _SYS_PWMSS_H_
|
||||
|
||||
/* SYS_PWMSS register set */
|
||||
typedef struct {
|
||||
|
||||
/***************************/
|
||||
/* PWM Subsystem Registers */
|
||||
/***************************/
|
||||
/* SYS_PWMSS_IDVER register bit field */
|
||||
union {
|
||||
volatile uint32_t IDVER;
|
||||
|
||||
volatile struct {
|
||||
unsigned Y_MINOR : 6; //5:0
|
||||
unsigned CUSTOM : 2; //7:6
|
||||
unsigned X_MAJOR : 3; //10:8
|
||||
unsigned R_RTL : 5; //15:11
|
||||
unsigned FUNC : 12; //27:16
|
||||
unsigned rsvd28 : 2; //29:28
|
||||
unsigned SCHEME : 2; //31:30
|
||||
} IDVER_bit;
|
||||
}; // 0x0
|
||||
|
||||
/* SYS_PWMSS_SYSCONFIG register bit field */
|
||||
union {
|
||||
volatile uint32_t SYSCONFIG;
|
||||
|
||||
volatile struct {
|
||||
unsigned SOFTRESET : 1; //0
|
||||
unsigned FREEEMU : 1; //1
|
||||
unsigned IDLEMODE : 2; //3:2
|
||||
unsigned STANDBYMODE : 2; //5:4
|
||||
unsigned rsvd6 : 26; //31:6
|
||||
} SYSCONFIG_bit;
|
||||
}; // 0x4
|
||||
|
||||
/* SYS_PWMSS_CLKCONFIG register bit field */
|
||||
union {
|
||||
volatile uint32_t CLKCONFIG;
|
||||
|
||||
volatile struct {
|
||||
unsigned ECAPCLK_EN : 1; //0
|
||||
unsigned ECAPCLKSTOP_REQ : 1; //1
|
||||
unsigned rsvd2 : 2; //3:2
|
||||
unsigned EQEPCLK_EN : 1; //4
|
||||
unsigned EQEPCLKSTOP_REQ : 1; //5
|
||||
unsigned rsvd6 : 2; //7:6
|
||||
unsigned EPWMCLK_EN : 1; //8
|
||||
unsigned EPWMCLKSTOP_REQ : 1; //9
|
||||
unsigned rsvd10 : 22; //31:10
|
||||
} CLKCONFIG_bit;
|
||||
}; // 0x8
|
||||
|
||||
/* SYS_PWMSS_CLKSTATUS register bit field */
|
||||
union {
|
||||
volatile uint32_t CLKSTATUS;
|
||||
|
||||
volatile struct {
|
||||
unsigned ECAPCLK_EN_ACK : 1; //0
|
||||
unsigned ECAPCLKSTOP_ACK : 1; //1
|
||||
unsigned rsvd2 : 2; //3:2
|
||||
unsigned EQEPCLK_EN_ACK : 1; //4
|
||||
unsigned EQEPCLKSTOP_ACK : 1; //5
|
||||
unsigned rsvd6 : 2; //7:6
|
||||
unsigned EPWMCLK_EN_ACK : 1; //8
|
||||
unsigned EPWMCLKSTOP_ACK : 1; //9
|
||||
unsigned rsvd10 : 22; //31:10
|
||||
} CLKSTATUS_bit;
|
||||
}; // 0xC
|
||||
|
||||
uint32_t rsvd10[60]; // 0x10 - 0xFC
|
||||
|
||||
/*************************/
|
||||
/* eCAP Module Registers */
|
||||
/*************************/
|
||||
/* SYS_PWMSS_ECAP_TSCTR register bit field */
|
||||
union {
|
||||
volatile uint32_t ECAP_TSCTR;
|
||||
|
||||
volatile struct {
|
||||
unsigned TSCTR : 32; //31:0
|
||||
} ECAP_TSCTR_bit;
|
||||
}; // 0x100
|
||||
|
||||
/* SYS_PWMSS_ECAP_CTRPHS register bit field */
|
||||
union {
|
||||
volatile uint32_t ECAP_CTRPHS;
|
||||
|
||||
volatile struct {
|
||||
unsigned CTRPHS : 32; //31:0
|
||||
} ECAP_CTRPHS_bit;
|
||||
}; // 0x104
|
||||
|
||||
/* SYS_PWMSS_ECAP_CAP1 register bit field */
|
||||
union {
|
||||
volatile uint32_t ECAP_CAP1;
|
||||
|
||||
volatile struct {
|
||||
unsigned CAP1 : 32; //31:0
|
||||
} ECAP_CAP1_bit;
|
||||
}; // 0x108
|
||||
|
||||
/* SYS_PWMSS_ECAP_CAP2 register bit field */
|
||||
union {
|
||||
volatile uint32_t ECAP_CAP2;
|
||||
|
||||
volatile struct {
|
||||
unsigned CAP2 : 32; //31:0
|
||||
} ECAP_CAP2_bit;
|
||||
}; // 0x10C
|
||||
|
||||
/* SYS_PWMSS_ECAP_CAP3 register bit field */
|
||||
union {
|
||||
volatile uint32_t ECAP_CAP3;
|
||||
|
||||
volatile struct {
|
||||
unsigned CAP3 : 32; //31:0
|
||||
} ECAP_CAP3_bit;
|
||||
}; // 0x110
|
||||
|
||||
/* SYS_PWMSS_ECAP_CAP4 register bit field */
|
||||
union {
|
||||
volatile uint32_t ECAP_CAP4;
|
||||
|
||||
volatile struct {
|
||||
unsigned CAP4 : 32; //31:0
|
||||
} ECAP_CAP4_bit;
|
||||
}; // 0x114
|
||||
|
||||
uint32_t rsvd118[4]; // 0x118 - 0x124
|
||||
|
||||
/* SYS_PWMSS_ECAP_ECCTL1 register bit field */
|
||||
volatile uint16_t ECAP_ECCTL1; // 0x128
|
||||
|
||||
/* SYS_PWMSS_ECAP_ECCTL2 register bit field */
|
||||
volatile uint16_t ECAP_ECCTL2; // 0x12A
|
||||
|
||||
/* SYS_PWMSS_ECAP_ECEINT register bit field */
|
||||
volatile uint16_t ECAP_ECEINT; // 0x12C
|
||||
|
||||
/* SYS_PWMSS_ECAP_ECFLG register bit field */
|
||||
volatile uint16_t ECAP_ECFLG; // 0x12E
|
||||
|
||||
/* SYS_PWMSS_ECAP_ECCLR register bit field */
|
||||
volatile uint16_t ECAP_ECCLR; // 0x130
|
||||
|
||||
/* SYS_PWMSS_ECAP_ECFRC register bit field */
|
||||
volatile uint16_t ECAP_ECFRC; // 0x132
|
||||
|
||||
uint32_t rsvd134[10]; // 0x134 - 0x158
|
||||
|
||||
/* SYS_PWMSS_ECAP_REVID register bit field */
|
||||
union {
|
||||
volatile uint32_t ECAP_REVID;
|
||||
|
||||
volatile struct {
|
||||
unsigned REV : 32; //31:0
|
||||
} ECAP_REVID_bit;
|
||||
}; // 0x15C
|
||||
|
||||
uint32_t rsvd160[8]; // 0x160 - 0x17C
|
||||
|
||||
/*************************/
|
||||
/* eQEP Module Registers */
|
||||
/*************************/
|
||||
/* SYS_PWMSS_EQEP_QPOSCNT register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_QPOSCNT;
|
||||
|
||||
volatile struct {
|
||||
unsigned QPOSCNT : 32; //31:0
|
||||
} EQEP_QPOSCNT_bit;
|
||||
}; // 0x180
|
||||
|
||||
/* SYS_PWMSS_EQEP_QPOSINIT register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_QPOSINIT;
|
||||
|
||||
volatile struct {
|
||||
unsigned QPOSINIT : 32; //31:0
|
||||
} EQEP_QPOSINIT_bit;
|
||||
}; // 0x184
|
||||
|
||||
/* SYS_PWMSS_EQEP_QPOSMAX register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_QPOSMAX;
|
||||
|
||||
volatile struct {
|
||||
unsigned QPOSMAX : 32; //31:0
|
||||
} EQEP_QPOSMAX_bit;
|
||||
}; // 0x188
|
||||
|
||||
/* SYS_PWMSS_EQEP_QPOSCMP register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_QPOSCMP;
|
||||
|
||||
volatile struct {
|
||||
unsigned QPOSCMP : 32; //31:0
|
||||
} EQEP_QPOSCMP_bit;
|
||||
}; // 0x18C
|
||||
|
||||
/* SYS_PWMSS_EQEP_QPOSILAT register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_QPOSILAT;
|
||||
|
||||
volatile struct {
|
||||
unsigned QPOSILAT : 32; //31:0
|
||||
} EQEP_QPOSILAT_bit;
|
||||
}; // 0x190
|
||||
|
||||
/* SYS_PWMSS_EQEP_QPOSSLAT register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_QPOSSLAT;
|
||||
|
||||
volatile struct {
|
||||
unsigned QPOSSLAT : 32; //31:0
|
||||
} EQEP_QPOSSLAT_bit;
|
||||
}; // 0x194
|
||||
|
||||
/* SYS_PWMSS_EQEP_QPOSLAT register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_QPOSLAT;
|
||||
|
||||
volatile struct {
|
||||
unsigned QPOSLAT : 32; //31:0
|
||||
} EQEP_QPOSLAT_bit;
|
||||
}; // 0x198
|
||||
|
||||
/* SYS_PWMSS_EQEP_QUTMR register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_QUTMR;
|
||||
|
||||
volatile struct {
|
||||
unsigned QUTMR : 32; //31:0
|
||||
} EQEP_QUTMR_bit;
|
||||
}; // 0x19C
|
||||
|
||||
/* SYS_PWMSS_EQEP_QUPRD register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_QUPRD;
|
||||
|
||||
volatile struct {
|
||||
unsigned QUPRD : 32; //31:0
|
||||
} EQEP_QUPRD_bit;
|
||||
}; // 0x1A0
|
||||
|
||||
/* SYS_PWMSS_EQEP_QWDTMR register bit field */
|
||||
volatile uint16_t EQEP_QWDTMR; // 0x1A4
|
||||
|
||||
/* SYS_PWMSS_EQEP_QWDPRD register bit field */
|
||||
volatile uint16_t EQEP_QWDPRD; // 0x1A6
|
||||
|
||||
/* SYS_PWMSS_EQEP_QDECCTL register bit field */
|
||||
volatile uint16_t EQEP_QDECCTL; // 0x1A8
|
||||
|
||||
/* SYS_PWMSS_EQEP_QEPCTL register bit field */
|
||||
volatile uint16_t EQEP_QEPCTL; // 0x1AA
|
||||
|
||||
/* SYS_PWMSS_EQEP_QCAPCTL register bit field */
|
||||
volatile uint16_t EQEP_QCAPCTL; // 0x1AC
|
||||
|
||||
/* SYS_PWMSS_EQEP_QPOSCTL register bit field */
|
||||
volatile uint16_t EQEP_QPOSCTL; // 0x1AE
|
||||
|
||||
/* SYS_PWMSS_EQEP_QEINT register bit field */
|
||||
volatile uint16_t EQEP_QEINT; // 0x1B0
|
||||
|
||||
/* SYS_PWMSS_EQEP_QFLG register bit field */
|
||||
volatile uint16_t EQEP_QFLG; // 0x1B2
|
||||
|
||||
/* SYS_PWMSS_EQEP_QCLR register bit field */
|
||||
volatile uint16_t EQEP_QCLR; // 0x1B4
|
||||
|
||||
/* SYS_PWMSS_EQEP_QFRC register bit field */
|
||||
volatile uint16_t EQEP_QFRC; // 0x1B6
|
||||
|
||||
/* SYS_PWMSS_EQEP_QEPSTS register bit field */
|
||||
volatile uint16_t EQEP_QEPSTS; // 0x1B8
|
||||
|
||||
/* SYS_PWMSS_EQEP_QCTMR register bit field */
|
||||
volatile uint16_t EQEP_QCTMR; // 0x1BA
|
||||
|
||||
/* SYS_PWMSS_EQEP_QCPRD register bit field */
|
||||
volatile uint16_t EQEP_QCPRD; // 0x1BC
|
||||
|
||||
/* SYS_PWMSS_EQEP_QCTMRLAT register bit field */
|
||||
volatile uint16_t EQEP_QCTMRLAT; // 0x1BE
|
||||
|
||||
/* SYS_PWMSS_EQEP_QCPRDLAT register bit field */
|
||||
volatile uint16_t EQEP_QCPRDLAT; // 0x1C0
|
||||
|
||||
uint16_t rsvd1C2[1]; // 0x1C2 - 0x1C3
|
||||
uint32_t rsvd1C4[6]; // 0x1C4 - 0x1D8
|
||||
|
||||
/* SYS_PWMSS_EQEP_REVID register bit field */
|
||||
union {
|
||||
volatile uint32_t EQEP_REVID;
|
||||
|
||||
volatile struct {
|
||||
unsigned REVID : 32; //31:0
|
||||
} EQEP_REVID_bit;
|
||||
}; // 0x1DC
|
||||
|
||||
uint32_t rsvd1E0[8]; // 0x1E0 - 0x1FC
|
||||
|
||||
/*************************/
|
||||
/* ePWM Module Registers */
|
||||
/*************************/
|
||||
/* SYS_PWMSS_EPWM_TBCTL register bit field */
|
||||
volatile uint16_t EPWM_TBCTL; // 0x200
|
||||
|
||||
/* SYS_PWMSS_EPWM_TBSTS register bit field */
|
||||
volatile uint16_t EPWM_TBSTS; // 0x202
|
||||
|
||||
/* SYS_PWMSS_EPWM_TBPHSHR register bit field */
|
||||
volatile uint16_t EPWM_TBPHSHR; // 0x204
|
||||
|
||||
/* SYS_PWMSS_EPWM_TBPHS register bit field */
|
||||
volatile uint16_t EPWM_TBPHS; // 0x206
|
||||
|
||||
/* SYS_PWMSS_EPWM_TBCNT register bit field */
|
||||
volatile uint16_t EPWM_TBCNT; // 0x208
|
||||
|
||||
/* SYS_PWMSS_EPWM_TBPRD register bit field */
|
||||
volatile uint16_t EPWM_TBPRD; // 0x20A
|
||||
|
||||
uint16_t rsvd20C[1]; // 0x20C - 0x20D
|
||||
|
||||
/* SYS_PWMSS_EPWM_CMPCTL register bit field */
|
||||
volatile uint16_t EPWM_CMPCTL; // 0x20E
|
||||
|
||||
/* SYS_PWMSS_EPWM_CMPAHR register bit field */
|
||||
volatile uint16_t EPWM_CMPAHR; // 0x210
|
||||
|
||||
/* SYS_PWMSS_EPWM_CMPA register bit field */
|
||||
volatile uint16_t EPWM_CMPA; // 0x212
|
||||
|
||||
/* SYS_PWMSS_EPWM_CMPB register bit field */
|
||||
volatile uint16_t EPWM_CMPB; // 0x214
|
||||
|
||||
/* SYS_PWMSS_EPWM_AQCTLA register bit field */
|
||||
volatile uint16_t EPWM_AQCTLA; // 0x216
|
||||
|
||||
/* SYS_PWMSS_EPWM_AQCTLB register bit field */
|
||||
volatile uint16_t EPWM_AQCTLB; // 0x218
|
||||
|
||||
/* SYS_PWMSS_EPWM_AQSFRC register bit field */
|
||||
volatile uint16_t EPWM_AQSFRC; // 0x21A
|
||||
|
||||
/* SYS_PWMSS_EPWM_AQCSFRC register bit field */
|
||||
volatile uint16_t EPWM_AQCSFRC; // 0x21C
|
||||
|
||||
/* SYS_PWMSS_EPWM_DBCTL register bit field */
|
||||
volatile uint16_t EPWM_DBCTL; // 0x21E
|
||||
|
||||
/* SYS_PWMSS_EPWM_DBRED register bit field */
|
||||
volatile uint16_t EPWM_DBRED; // 0x220
|
||||
|
||||
/* SYS_PWMSS_EPWM_DBFED register bit field */
|
||||
volatile uint16_t EPWM_DBFED; // 0x222
|
||||
|
||||
/* SYS_PWMSS_EPWM_TZSEL register bit field */
|
||||
volatile uint16_t EPWM_TZSEL; // 0x224
|
||||
|
||||
uint16_t rsvd226[1]; // 0x226 - 0x227
|
||||
|
||||
/* SYS_PWMSS_EPWM_TZCTL register bit field */
|
||||
volatile uint16_t EPWM_TZCTL; // 0x228
|
||||
|
||||
/* SYS_PWMSS_EPWM_TZEINT register bit field */
|
||||
volatile uint16_t EPWM_TZEINT; // 0x22A
|
||||
|
||||
/* SYS_PWMSS_EPWM_TZFLG register bit field */
|
||||
volatile uint16_t EPWM_TZFLG; // 0x22C
|
||||
|
||||
/* SYS_PWMSS_EPWM_TZCLR register bit field */
|
||||
volatile uint16_t EPWM_TZCLR; // 0x22E
|
||||
|
||||
/* SYS_PWMSS_EPWM_TZFRC register bit field */
|
||||
volatile uint16_t EPWM_TZFRC; // 0x230
|
||||
|
||||
/* SYS_PWMSS_EPWM_ETSEL register bit field */
|
||||
volatile uint16_t EPWM_ETSEL; // 0x232
|
||||
|
||||
/* SYS_PWMSS_EPWM_ETPS register bit field */
|
||||
volatile uint16_t EPWM_ETPS; // 0x234
|
||||
|
||||
/* SYS_PWMSS_EPWM_ETFLG register bit field */
|
||||
volatile uint16_t EPWM_ETFLG; // 0x236
|
||||
|
||||
/* SYS_PWMSS_EPWM_ETCLR register bit field */
|
||||
volatile uint16_t EPWM_ETCLR; // 0x238
|
||||
|
||||
/* SYS_PWMSS_EPWM_ETFRC register bit field */
|
||||
volatile uint16_t EPWM_ETFRC; // 0x23A
|
||||
|
||||
/* SYS_PWMSS_EPWM_PCCTL register bit field */
|
||||
volatile uint16_t EPWM_PCCTL; // 0x23C
|
||||
|
||||
uint16_t rsvd23E[1]; // 0x23E - 0x23F
|
||||
uint32_t rsvd240[32]; // 0x240 - 0x2BC
|
||||
|
||||
/* SYS_PWMSS_EPWM_HRCNGF register bit field */
|
||||
volatile uint16_t EPWM_HRCNGF; // 0x2C0
|
||||
|
||||
} sysPwmss;
|
||||
|
||||
volatile __far sysPwmss PWMSS0 __attribute__((cregister("PWMSS0", far), peripheral));
|
||||
volatile __far sysPwmss PWMSS1 __attribute__((cregister("PWMSS1", far), peripheral));
|
||||
volatile __far sysPwmss PWMSS2 __attribute__((cregister("PWMSS2", far), peripheral));
|
||||
|
||||
#endif /* _SYS_PWMSS_H_ */
|
|
@ -0,0 +1,268 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* File : pru_rpmsg.h
|
||||
*
|
||||
* Summary : An RPMsg interface for the PRU to use while communicating with
|
||||
* the ARM host.
|
||||
*
|
||||
* Notes :
|
||||
* - This file creates a structure (pru_rpmsg_transport) that contains
|
||||
* pointers to two pru_virtqueue structures. This structure is used as the
|
||||
* underlying transport layer of all RPMsg communication. Only one
|
||||
* pru_rpmsg_transport structure is needed because multiple logical channels
|
||||
* can use the same underlying transport.
|
||||
* - This pru_rpmsg interface is meant to sit on top of the pru_virtqueue
|
||||
* interface and abstract the communication even further away from the
|
||||
* underlying data structures. The goal is to make the communication as
|
||||
* simple as possible at the user application level.
|
||||
* - The logic for the PRU side is summarized below:
|
||||
*
|
||||
* PRU Slave:
|
||||
* - To receive buffer from the ARM host:
|
||||
* pru_rpmsg_receive(*transport, *src, *dst, *data, *len);
|
||||
* - To send buffer to the host:
|
||||
* pru_rpmsg_send(*transport, src, dst, *data, len);
|
||||
*/
|
||||
|
||||
#ifndef _PRU_RPMSG_H_
|
||||
#define _PRU_RPMSG_H_
|
||||
|
||||
#include <pru_virtqueue.h>
|
||||
#include <pru_virtio_ring.h>
|
||||
|
||||
/* Return value indicating no kick was sent */
|
||||
#define PRU_RPMSG_NO_KICK 1
|
||||
/* Return value indicating success */
|
||||
#define PRU_RPMSG_SUCCESS 0
|
||||
/* Return value indicating there were no available buffers */
|
||||
#define PRU_RPMSG_NO_BUF_AVAILABLE -1
|
||||
/* Return value indicating that the buffer from the virtqueue was too small */
|
||||
#define PRU_RPMSG_BUF_TOO_SMALL -2
|
||||
/* Return value indicating that an invalid head index was given */
|
||||
#define PRU_RPMSG_INVALID_HEAD -3
|
||||
/* Return value indication that an invalid event number was given */
|
||||
#define PRU_RPMSG_INVALID_EVENT -4
|
||||
|
||||
/* Max PRU-ICSS system event number for pru_mst_intr */
|
||||
#define MAX_VALID_EVENT 31
|
||||
/* Min PRU-ICSS system event number for pru_mst_intr */
|
||||
#define MIN_VALID_EVENT 16
|
||||
|
||||
/* The maximum size of the channel name and description */
|
||||
#define RPMSG_NAME_SIZE 32
|
||||
/* The maximum size of the buffer (including the header) */
|
||||
#define RPMSG_BUF_SIZE 512
|
||||
|
||||
enum pru_rpmsg_ns_flags {
|
||||
RPMSG_NS_CREATE = 0,
|
||||
RPMSG_NS_DESTROY = 1
|
||||
};
|
||||
|
||||
/**
|
||||
* Summary : pru_rpmsg_transport is a structure that groups together the
|
||||
* two pru_virtqueues that are needed for two-way communication
|
||||
* with the ARM. This structure provides a logical wrapper for
|
||||
* the transport layer of the application. NOTE: Multiple
|
||||
* (logical) channels can be implemented on top of the same
|
||||
* transport layer.
|
||||
*
|
||||
* Variables : virtqueue0: contains the pru_virtqueue that is used for the
|
||||
* PRU->ARM communication
|
||||
* virtqueue1: contains the pru_virtqueue that is used for
|
||||
* the ARM->PRU communication
|
||||
*/
|
||||
struct pru_rpmsg_transport {
|
||||
struct pru_virtqueue virtqueue0;
|
||||
struct pru_virtqueue virtqueue1;
|
||||
};
|
||||
|
||||
/**
|
||||
* Summary : pru_rpmsg_init initializes the underlying transport layer
|
||||
* data structures.
|
||||
*
|
||||
* Parameters : transport: a pointer to the transport data structure that
|
||||
* contains the underlying data structures to be
|
||||
* initialized
|
||||
* vring0: a pointer to vring0 which is provided by the ARM
|
||||
* core through the resource table
|
||||
* vring1: a pointer to vring1 which is provided by the ARM
|
||||
* core through the resource table
|
||||
* to_arm_event: the number of the PRU-ICSS system event
|
||||
* that is specified in the device tree that
|
||||
* is used to 'kick' the ARM core
|
||||
* from_arm_event: the number of the PRU-ICSS system event
|
||||
* that is specified in the device tree
|
||||
* that is used to receive 'kicks' from the
|
||||
* ARM core
|
||||
*
|
||||
* Description : pru_rpmsg_init takes the vrings and the events provided
|
||||
* through the resource table and initializes the transport
|
||||
* layer. Once this function call is successful RPMsg
|
||||
* channels can be created and used.
|
||||
*
|
||||
* Return Value : Returns PRU_RPMSG_INVALID_EVENT if the values provided
|
||||
* in to_arm_event or from_arm_event are outside of the
|
||||
* allowable range of events. Returns PRU_RPMSG_SUCCESS
|
||||
* if the initialization is successful.
|
||||
*/
|
||||
int16_t pru_rpmsg_init(
|
||||
struct pru_rpmsg_transport *transport,
|
||||
struct fw_rsc_vdev_vring *vring0,
|
||||
struct fw_rsc_vdev_vring *vring1,
|
||||
uint32_t to_arm_event,
|
||||
uint32_t from_arm_event
|
||||
);
|
||||
|
||||
/**
|
||||
* Summary : pru_rpmsg_receive receives a message, if available, from
|
||||
* the ARM host.
|
||||
*
|
||||
* Parameters : transport: a pointer to the transport layer from which the
|
||||
* message should be received
|
||||
* src: a pointer that is populated with the source address
|
||||
* where the message originated
|
||||
* dst: a pointer that is populated with the destination
|
||||
* address where the message was sent (can help determine
|
||||
* for which channel the message is intended on the PRU)
|
||||
* data: a pointer that is populated with a local data buffer
|
||||
* containing the message payload
|
||||
* len: a pointer that is populated with the length of the
|
||||
* message payload
|
||||
*
|
||||
* Description : pru_rpmsg_receive uses the pru_virtqueue interface to get
|
||||
* an available buffer, copy the buffer into local memory,
|
||||
* add the buffer as a used buffer to the vring, and then kick
|
||||
* the remote processor if necessary. The src, dst, data, and
|
||||
* len pointers are populated with the information about the
|
||||
* message and local buffer data if the reception is
|
||||
* successful.
|
||||
*
|
||||
* Return Value : Returns PRU_RPMSG_NO_BUF_AVAILABLE if there is currently no
|
||||
* buffer available for receive. Returns PRU_RPMSG_INVALID_HEAD
|
||||
* if the head index returned for the available buffer is
|
||||
* invalid. Returns PRU_RPMSG_SUCCESS if the message is
|
||||
* successfully received.
|
||||
*/
|
||||
int16_t pru_rpmsg_receive(
|
||||
struct pru_rpmsg_transport *transport,
|
||||
uint16_t *src,
|
||||
uint16_t *dst,
|
||||
void *data,
|
||||
uint16_t *len
|
||||
);
|
||||
|
||||
/**
|
||||
* Summary : pru_rpmsg_send sends a message to the ARM host using the
|
||||
* virtqueues in the pru_rpmsg_transport structure. The
|
||||
* source and destination address of the message are passed
|
||||
* in as parameters to the function. The data to be sent and
|
||||
* its length are passed in the data and len parameters.
|
||||
*
|
||||
* Parameters : transport: a pointer to the transport layer from which the
|
||||
* message should be sent
|
||||
* src: the source address where this message will originate
|
||||
* dst: the destination address where the message will be sent
|
||||
* data: a pointer to a local data buffer containing the
|
||||
* message payload
|
||||
* len: the length of the message payload
|
||||
*
|
||||
* Description : pru_rpmsg_send sends a message to the src parameter and
|
||||
* from the dst parameter. The transport structure defines the
|
||||
* underlying transport mechanism that will be used. The
|
||||
* data parameter is a pointer to a local buffer that should
|
||||
* be sent to the destination address and the len parameter is
|
||||
* the length of that buffer.
|
||||
*
|
||||
* Return Value : Returns PRU_RPMSG_NO_BUF_AVAILABLE if there is currently no
|
||||
* buffer available for send. Returns PRU_RPMSG_BUF_TOO_SMALL
|
||||
* if the buffer from the vring is too small to hold the
|
||||
* message payload being sent. Returns PRU_RPMSG_INVALID_HEAD
|
||||
* if the head index returned for the send buffer is invalid.
|
||||
* Returns PRU_RPMSG_SUCCESS if the message is successfully
|
||||
* sent.
|
||||
*/
|
||||
int16_t pru_rpmsg_send(
|
||||
struct pru_rpmsg_transport *transport,
|
||||
uint32_t src,
|
||||
uint32_t dst,
|
||||
void *data,
|
||||
uint16_t len
|
||||
);
|
||||
|
||||
/**
|
||||
* Summary : pru_rpmsg_channel uses an RPMsg Name Service Announcment
|
||||
* to either create or destroy an RPMsg channel depending on
|
||||
* the pru_rpmsg_ns_flags parameter that is specified.
|
||||
*
|
||||
* Parameters : flags: an enum that is used to create (RPMSG_NS_CREATE) or
|
||||
* destroy (RPMSG_NS_DESTROY) an RPMsg channel
|
||||
* transport: a pointer to the transport layer on which this
|
||||
* Name Service Announcement will be sent
|
||||
* name: the name of the channel being created or destroyed
|
||||
* ******* The name of the channel is very important as
|
||||
* ******* it is the method that Linux on the ARM uses
|
||||
* ******* to connect a PRU firmware with a corresponding
|
||||
* ******* Linux driver
|
||||
* desc: the description of the RPMsg channel being created
|
||||
* or destroyed
|
||||
* port: the local source address of the RPMsg channel. This
|
||||
* is the address where PRU messages destined for the
|
||||
* ARM host will originate
|
||||
*
|
||||
* Description : pru_rpmsg_channel sends a message letting the ARM
|
||||
* host know that a channel is to be created or destroyed. If
|
||||
* a channel is to be created then this message will notify
|
||||
* the name server on the ARM host to create a new channel. If
|
||||
* a channel is to be destroyed this will tear down this
|
||||
* logical channel of communication between the PRU and the
|
||||
* ARM host.
|
||||
*
|
||||
* Return Value : Returns PRU_RPMSG_NO_BUF_AVAILABLE if there is currently no
|
||||
* buffer available for send. Returns PRU_RPMSG_BUF_TOO_SMALL
|
||||
* if the buffer from the vring is too small to hold the
|
||||
* message payload being sent. Returns PRU_RPMSG_INVALID_HEAD
|
||||
* if the head index returned for the send buffer is invalid.
|
||||
* Returns PRU_RPMSG_SUCCESS if the message is successfully
|
||||
* sent.
|
||||
*/
|
||||
int16_t pru_rpmsg_channel(
|
||||
enum pru_rpmsg_ns_flags flags,
|
||||
struct pru_rpmsg_transport *transport,
|
||||
char *name,
|
||||
char *desc,
|
||||
int32_t port
|
||||
);
|
||||
|
||||
#endif /* _PRU_RPMSG_H_ */
|
|
@ -0,0 +1,83 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _PRU_TYPES_H_
|
||||
#define _PRU_TYPES_H_
|
||||
|
||||
/* Custom Resource info: Must match drivers/remoteproc/pru_rproc.h */
|
||||
#define TYPE_PRU_INTS 1
|
||||
|
||||
/**
|
||||
* struct ch_map - sysevts-to-channel mapping
|
||||
*
|
||||
* @evt: the number of the sysevt
|
||||
* @ch: channel number assigned to a given @sysevt
|
||||
*
|
||||
* PRU system events are mapped to channels, and these channels are mapped to
|
||||
* hosts. Events can be mapped to channels in a one-to-one or many-to-one ratio
|
||||
* (multiple events per channel), and channels can be mapped to hosts in a
|
||||
* one-to-one or many-to-one ratio (multiple events per channel).
|
||||
*
|
||||
* @evt is the number of the sysevt, and @ch is the number of the channel to be
|
||||
* mapped.
|
||||
*/
|
||||
|
||||
struct ch_map {
|
||||
uint8_t evt;
|
||||
uint8_t ch;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fw_rsc_custom_ints - custom resource to define PRU interrupts
|
||||
* @version: revision number of the custom ints type
|
||||
* @channel_host: assignment of PRU channels to hosts
|
||||
* @num_evts: device address of INTC
|
||||
* @event_channel: mapping of sysevts to channels
|
||||
*
|
||||
* PRU system events are mapped to channels, and these channels are mapped to
|
||||
* hosts. Events can be mapped to channels in a one-to-one or many-to-one ratio
|
||||
* (multiple events per channel), and channels can be mapped to hosts in a
|
||||
* one-to-one or many-to-one ratio (multiple events per channel).
|
||||
*
|
||||
* @da is the device address of the interrupt controller, @channel_map is
|
||||
* used to specify to which channel, if any, an event is mapped, and @host_map
|
||||
* specifies to which host, if any, a channel is mapped.
|
||||
*/
|
||||
struct fw_rsc_custom_ints {
|
||||
uint16_t version;
|
||||
uint8_t channel_host[10];
|
||||
uint32_t num_evts;
|
||||
struct ch_map *event_channel;
|
||||
};
|
||||
|
||||
#endif /* _PRU_TYPES_H_ */
|
|
@ -0,0 +1,42 @@
|
|||
#ifndef _LINUX_VIRTIO_IDS_H
|
||||
#define _LINUX_VIRTIO_IDS_H
|
||||
/*
|
||||
* Virtio IDs
|
||||
*
|
||||
* This header is BSD licensed so anyone can use the definitions to implement
|
||||
* compatible drivers/servers.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of IBM nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE. */
|
||||
|
||||
#define VIRTIO_ID_NET 1 /* virtio net */
|
||||
#define VIRTIO_ID_BLOCK 2 /* virtio block */
|
||||
#define VIRTIO_ID_CONSOLE 3 /* virtio console */
|
||||
#define VIRTIO_ID_RNG 4 /* virtio rng */
|
||||
#define VIRTIO_ID_BALLOON 5 /* virtio balloon */
|
||||
#define VIRTIO_ID_RPMSG 7 /* virtio remote processor messaging */
|
||||
#define VIRTIO_ID_SCSI 8 /* virtio scsi */
|
||||
#define VIRTIO_ID_9P 9 /* 9p virtio console */
|
||||
#define VIRTIO_ID_RPROC_SERIAL 11 /* virtio remoteproc serial link */
|
||||
|
||||
#endif /* _LINUX_VIRTIO_IDS_H */
|
|
@ -0,0 +1,163 @@
|
|||
#ifndef _UAPI_LINUX_VIRTIO_RING_H
|
||||
#define _UAPI_LINUX_VIRTIO_RING_H
|
||||
/* An interface for efficient virtio implementation, currently for use by KVM
|
||||
* and lguest, but hopefully others soon. Do NOT change this since it will
|
||||
* break existing servers and clients.
|
||||
*
|
||||
* This header is BSD licensed so anyone can use the definitions to implement
|
||||
* compatible drivers/servers.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of IBM nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL IBM OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Copyright Rusty Russell IBM Corporation 2007. */
|
||||
#include <stdint.h>
|
||||
|
||||
/* This marks a buffer as continuing via the next field. */
|
||||
#define VRING_DESC_F_NEXT 1
|
||||
/* This marks a buffer as write-only (otherwise read-only). */
|
||||
#define VRING_DESC_F_WRITE 2
|
||||
/* This means the buffer contains a list of buffer descriptors. */
|
||||
#define VRING_DESC_F_INDIRECT 4
|
||||
|
||||
/* The Host uses this in used->flags to advise the Guest: don't kick me when
|
||||
* you add a buffer. It's unreliable, so it's simply an optimization. Guest
|
||||
* will still kick if it's out of buffers. */
|
||||
#define VRING_USED_F_NO_NOTIFY 1
|
||||
/* The Guest uses this in avail->flags to advise the Host: don't interrupt me
|
||||
* when you consume a buffer. It's unreliable, so it's simply an
|
||||
* optimization. */
|
||||
#define VRING_AVAIL_F_NO_INTERRUPT 1
|
||||
|
||||
/* We support indirect buffer descriptors */
|
||||
#define VIRTIO_RING_F_INDIRECT_DESC 28
|
||||
|
||||
/* The Guest publishes the used index for which it expects an interrupt
|
||||
* at the end of the avail ring. Host should ignore the avail->flags field. */
|
||||
/* The Host publishes the avail index for which it expects a kick
|
||||
* at the end of the used ring. Guest should ignore the used->flags field. */
|
||||
#define VIRTIO_RING_F_EVENT_IDX 29
|
||||
|
||||
/* Virtio ring descriptors: 16 bytes. These can chain together via "next". */
|
||||
struct vring_desc {
|
||||
/* Address (guest-physical). */
|
||||
uint64_t addr;
|
||||
/* Length. */
|
||||
uint32_t len;
|
||||
/* The flags as indicated above. */
|
||||
uint16_t flags;
|
||||
/* We chain unused descriptors via this, too */
|
||||
uint16_t next;
|
||||
};
|
||||
|
||||
struct vring_avail {
|
||||
uint16_t flags;
|
||||
uint16_t idx;
|
||||
uint16_t ring[];
|
||||
};
|
||||
|
||||
/* u32 is used here for ids for padding reasons. */
|
||||
struct vring_used_elem {
|
||||
/* Index of start of used descriptor chain. */
|
||||
uint32_t id;
|
||||
/* Total length of the descriptor chain which was used (written to) */
|
||||
uint32_t len;
|
||||
};
|
||||
|
||||
struct vring_used {
|
||||
uint16_t flags;
|
||||
uint16_t idx;
|
||||
struct vring_used_elem ring[];
|
||||
};
|
||||
|
||||
struct vring {
|
||||
uint32_t num;
|
||||
|
||||
struct vring_desc *desc;
|
||||
|
||||
struct vring_avail *avail;
|
||||
|
||||
struct vring_used *used;
|
||||
};
|
||||
|
||||
/* The standard layout for the ring is a continuous chunk of memory which looks
|
||||
* like this. We assume num is a power of 2.
|
||||
*
|
||||
* struct vring
|
||||
* {
|
||||
* // The actual descriptors (16 bytes each)
|
||||
* struct vring_desc desc[num];
|
||||
*
|
||||
* // A ring of available descriptor heads with free-running index.
|
||||
* __u16 avail_flags;
|
||||
* __u16 avail_idx;
|
||||
* __u16 available[num];
|
||||
* __u16 used_event_idx;
|
||||
*
|
||||
* // Padding to the next align boundary.
|
||||
* char pad[];
|
||||
*
|
||||
* // A ring of used descriptor heads with free-running index.
|
||||
* __u16 used_flags;
|
||||
* __u16 used_idx;
|
||||
* struct vring_used_elem used[num];
|
||||
* __u16 avail_event_idx;
|
||||
* };
|
||||
*/
|
||||
/* We publish the used event index at the end of the available ring, and vice
|
||||
* versa. They are at the end for backwards compatibility. */
|
||||
#define vring_used_event(vr) ((vr)->avail->ring[(vr)->num])
|
||||
#define vring_avail_event(vr) (*(__u16 *)&(vr)->used->ring[(vr)->num])
|
||||
|
||||
static inline void vring_init(struct vring *vr, uint32_t num, void *p,
|
||||
uint64_t align)
|
||||
{
|
||||
vr->num = num;
|
||||
vr->desc = p;
|
||||
vr->avail = (void *)((char *)p + num*sizeof(struct vring_desc));
|
||||
vr->used = (void *)(uintptr_t)(((uintptr_t)&vr->avail->ring[num]
|
||||
+ sizeof(uint16_t) + align-1) & ~(align - 1));
|
||||
}
|
||||
|
||||
static inline unsigned vring_size(uint16_t num, uint64_t align)
|
||||
{
|
||||
return ((sizeof(struct vring_desc) * num + sizeof(uint16_t) * (3 + num)
|
||||
+ align - 1) & ~(align - 1))
|
||||
+ sizeof(uint16_t) * 3 + sizeof(struct vring_used_elem) * num;
|
||||
}
|
||||
|
||||
/* The following is used with USED_EVENT_IDX and AVAIL_EVENT_IDX */
|
||||
/* Assuming a given event_idx value from the other size, if
|
||||
* we have just incremented index from old to new_idx,
|
||||
* should we trigger an event? */
|
||||
static inline int vring_need_event(uint16_t event_idx, uint16_t new_idx, uint16_t old)
|
||||
{
|
||||
/* Note: Xen has similar logic for notification hold-off
|
||||
* in include/xen/interface/io/ring.h with req_event and req_prod
|
||||
* corresponding to event_idx + 1 and new_idx respectively.
|
||||
* Note also that req_event and req_prod in Xen start at 1,
|
||||
* event indexes in virtio start at 0. */
|
||||
return (uint16_t)(new_idx - event_idx - 1) < (uint16_t)(new_idx - old);
|
||||
}
|
||||
|
||||
#endif /* _UAPI_LINUX_VIRTIO_RING_H */
|
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* File : pru_virtqueue.h
|
||||
*
|
||||
* Summary : A virtual queue interface to simplify vring usage.
|
||||
*
|
||||
* Notes :
|
||||
* - This file implements the vring functions needed by the PRU core
|
||||
* - The PRU core is considered the slave and the ARM core is considered the
|
||||
* host
|
||||
* - The ARM host always adds *available* buffers to send/receive, while the
|
||||
* PRU slave always adds *used* buffers to send/receive.
|
||||
* - The logic for the PRU side is summarized below:
|
||||
*
|
||||
* PRU Slave:
|
||||
* - To receive buffer from the ARM host:
|
||||
* virtqueue_getAvailBuf(vq_slave);
|
||||
* >> empty data from buf <<
|
||||
* virtqueue_addUsedBuf(vq_slave);
|
||||
* virtqueue_kick(vq_slave);
|
||||
* - To send buffer to the host:
|
||||
* virtqueue_getAvailBuf(vq_host);
|
||||
* >> copy data into buf <<
|
||||
* virtqueue_addUsedBuf(vq_host);
|
||||
* virtqueue_kick(vq_host);
|
||||
*/
|
||||
|
||||
#ifndef _PRU_VIRTQUEUE_H_
|
||||
#define _PRU_VIRTQUEUE_H_
|
||||
|
||||
#include <rsc_types.h>
|
||||
#include <pru_virtio_ring.h>
|
||||
|
||||
/* Return value indicating no kick was sent */
|
||||
#define PRU_VIRTQUEUE_NO_KICK 1
|
||||
/* Return value indicating success */
|
||||
#define PRU_VIRTQUEUE_SUCCESS 0
|
||||
/* Return value indicating there were no available buffers */
|
||||
#define PRU_VIRTQUEUE_NO_BUF_AVAILABLE -1
|
||||
/* Return value indicating that an invalid head index was given */
|
||||
#define PRU_VIRTQUEUE_INVALID_HEAD -2
|
||||
|
||||
/**
|
||||
* Summary : pru_virtqueue is a structure that encapsulates everything
|
||||
* needed for a 'virtual queue'. This structure wraps a vring
|
||||
* with extra information that is needed by the application
|
||||
* in order to use the vring.
|
||||
*
|
||||
* Variables : id: The notification ID of the vring.
|
||||
* to_arm_event: The PRU-ICSS system event that signals the ARM.
|
||||
* from_arm_event: The PRU-ICSS system event that the ARM uses to
|
||||
* signal the PRU.
|
||||
* last_avail_idx: A local running counter that is used by the
|
||||
* PRU to determine whether or not a new
|
||||
* available buffer has been added to the
|
||||
* vring.
|
||||
* vring: The underlying virtio structure that is being used
|
||||
* to pass buffers back and forth between the ARM and
|
||||
* PRU. See pru_virtio_ring.h.
|
||||
*/
|
||||
struct pru_virtqueue {
|
||||
uint32_t id;
|
||||
uint32_t to_arm_event;
|
||||
uint32_t from_arm_event;
|
||||
uint16_t last_avail_idx;
|
||||
struct vring vring;
|
||||
};
|
||||
|
||||
/**
|
||||
* Summary : pru_virtqueue_init initializes the pru_virtqueue structure
|
||||
* with values from the resource table.
|
||||
*
|
||||
* Parameters : vq: a pointer to a pru_virtqueue structure that will be
|
||||
* initialized
|
||||
* vring: a pointer to a vring that is populated and returned
|
||||
* by the ARM host through the resource table (the id,
|
||||
* number of descriptors, address of the vring, and
|
||||
* alignment information are contained in this vring
|
||||
* pointer's structure
|
||||
* to_arm_event: the PRU-ICSS system event to trigger in order to
|
||||
* 'kick' the ARM host when sending data
|
||||
* from_arm_event: the PRU-ICSS system event to check
|
||||
* for data arriving from the ARM host
|
||||
*
|
||||
* Description : This function initializes the pru_virtqueue (vq) with input
|
||||
* values from the vring in the resource table. This function
|
||||
* should be called once for each virtqueue/vring. After
|
||||
* initialization the pru_virtqueue pointer, vq, should be
|
||||
* passed to the other functions in this header file.
|
||||
*
|
||||
* Return Value : No return value.
|
||||
*/
|
||||
void pru_virtqueue_init(
|
||||
struct pru_virtqueue *vq,
|
||||
struct fw_rsc_vdev_vring *vring,
|
||||
uint32_t to_arm_event,
|
||||
uint32_t from_arm_event
|
||||
);
|
||||
|
||||
/**
|
||||
* Summary : pru_virtqueue_get_avail_buf - gets the next available
|
||||
* buffer from the pru_virtqueue specified in vq.
|
||||
*
|
||||
* Parameters : vq: pointer to the pru_virtqueue from which the available
|
||||
* buffer should be retrieved
|
||||
* buf: pointer to be filled with the address of the available
|
||||
* buffer
|
||||
* len: pointer to be filled with the length of the available
|
||||
* buffer
|
||||
*
|
||||
* Description : This function compares our last_avail_idx running counter
|
||||
* against the vring.avail->idx value to see if there is a
|
||||
* buffer available that we have not used. If our last
|
||||
* available index running counter matches the vring.avail->idx
|
||||
* value then there have been no new available buffers added
|
||||
* by the host. If the two indices do not match then the host
|
||||
* has added new buffers and and we can set @buf to point to
|
||||
* the available buffer and @len to match the available buffers
|
||||
* length. If an available buffer is found we increment out
|
||||
* last_avail_idx to show that we used another buffer.
|
||||
*
|
||||
* Return Value : PRU_VIRTQUEUE_NO_BUF_AVAILABLE if no buffer available.
|
||||
* Returns the vring.desc index of the available buffer
|
||||
* otherwise.
|
||||
*/
|
||||
int16_t pru_virtqueue_get_avail_buf(
|
||||
struct pru_virtqueue *vq,
|
||||
void **buf,
|
||||
uint32_t *len
|
||||
);
|
||||
|
||||
/**
|
||||
* Summary : pru_virtqueue_add_used_buf adds a used buffer to the
|
||||
* pru_virtqueue specified in vq.
|
||||
*
|
||||
* Parameters : vq: pointer to the pru_virtqueue where the used buffer
|
||||
* should be added
|
||||
* head: vring.desc[] index of the used buffer
|
||||
* len: length of the used buffer being added
|
||||
*
|
||||
* Description : This function makes sure that the head vring.desc index
|
||||
* (head) is a valid index. If the index is valid, then the
|
||||
* buffer is added to the used list in the vring contained by
|
||||
* the pru_virtqueue (vq).
|
||||
*
|
||||
* Return Value : PRU_VIRTQUEUE_INVALID_HEAD if head is an invalid index for
|
||||
* the vring.desc array. Returns PRU_VIRTQUEUE_SUCCESS
|
||||
* otherwise.
|
||||
*/
|
||||
int16_t pru_virtqueue_add_used_buf(
|
||||
struct pru_virtqueue *vq,
|
||||
int16_t head,
|
||||
uint32_t len
|
||||
);
|
||||
|
||||
/**
|
||||
* Summary : pru_virtqueue_kick sends a notification to the remote
|
||||
* processor that the PRU has added a buffer to the
|
||||
* pru_virtqueue.
|
||||
*
|
||||
* Parameters : vq: pointer to the pru_virtqueue that is to be kicked
|
||||
*
|
||||
* Description : This function is used by the PRU to notify the ARM host in
|
||||
* two situations:
|
||||
* 1. That the PRU has consumed a buffer that the ARM
|
||||
* host sent through the slave pru_virtqueue
|
||||
* 2. That the PRU has sent a buffer to the ARM through
|
||||
* the host pru_virtqueue
|
||||
* If the pru_virtqueue's VRING_AVAIL_F_NO_INTERRUPT flag is
|
||||
* set then the pru does not kick the pru_virtqueue.
|
||||
*
|
||||
* Return Value : PRU_VIRTQUEUE_NO_KICK if the VRING_AVAIL_F_NO_INTERRUPT
|
||||
* flag is set or PRU_VIRTQUEUE_SUCCESS otherwise.
|
||||
*/
|
||||
int16_t pru_virtqueue_kick(
|
||||
struct pru_virtqueue *vq
|
||||
);
|
||||
|
||||
#endif /* _PRU_VIRTQUEUE_H_ */
|
|
@ -0,0 +1,347 @@
|
|||
/*
|
||||
* Copyright(c) 2011 Texas Instruments, Inc.
|
||||
* Copyright(c) 2011 Google, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name Texas Instruments nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _RSC_TYPES_H_
|
||||
#define _RSC_TYPES_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <pru_types.h>
|
||||
|
||||
/* Size constants must match those used on host */
|
||||
#define SZ_4K (0x00001000)
|
||||
#define SZ_8K (0x00002000)
|
||||
|
||||
/* Resource info: Must match include/linux/remoteproc.h: */
|
||||
#define TYPE_CARVEOUT 0
|
||||
#define TYPE_DEVMEM 1
|
||||
#define TYPE_TRACE 2
|
||||
#define TYPE_VDEV 3
|
||||
#define TYPE_INTMEM 4
|
||||
#define TYPE_CUSTOM 5
|
||||
|
||||
union fw_custom {
|
||||
/* add custom resources here */
|
||||
struct fw_rsc_custom_ints pru_ints;
|
||||
/* maintain reserved as the last element */
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
/* Common Resource Structure Types */
|
||||
|
||||
/**
|
||||
* struct resource_table - firmware resource table header
|
||||
* @ver: version number
|
||||
* @num: number of resource entries
|
||||
* @reserved: reserved (must be zero)
|
||||
*
|
||||
* A resource table is essentially a list of system resources required
|
||||
* by the remote processor. It may also include configuration entries.
|
||||
* If needed, the remote processor firmware should contain this table
|
||||
* as a dedicated ".resource_table" ELF section.
|
||||
*
|
||||
* Some resources entries are mere announcements, where the host is informed
|
||||
* of specific remoteproc configuration. Other entries require the host to
|
||||
* do something (e.g. allocate a system resource). Sometimes a negotiation
|
||||
* is expected, where the firmware requests a resource, and once allocated,
|
||||
* the host should provide back its details (e.g. address of an allocated
|
||||
* memory region).
|
||||
*
|
||||
* The header of the resource table, as expressed by this structure,
|
||||
* contains a version number (should we need to change this format in the
|
||||
* future), the number of available resource entries, and their offsets
|
||||
* in the table.
|
||||
*
|
||||
* Immediately following this header are the resource entries themselves,
|
||||
* each of which begins with a resource entry header (as described below).
|
||||
*/
|
||||
struct resource_table {
|
||||
uint32_t ver;
|
||||
uint32_t num;
|
||||
uint32_t reserved[2];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fw_rsc_carveout - physically contiguous memory request
|
||||
* @type: type of resource
|
||||
* @da: device address
|
||||
* @pa: physical address
|
||||
* @len: length (in bytes)
|
||||
* @flags: iommu protection flags
|
||||
* @reserved: reserved (must be zero)
|
||||
* @name: human-readable name of the requested memory region
|
||||
*
|
||||
* This resource entry requests the host to allocate a physically contiguous
|
||||
* memory region.
|
||||
*
|
||||
* These request entries should precede other firmware resource entries,
|
||||
* as other entries might request placing other data objects inside
|
||||
* these memory regions (e.g. data/code segments, trace resource entries, ...).
|
||||
*
|
||||
* Allocating memory this way helps utilizing the reserved physical memory
|
||||
* (e.g. CMA) more efficiently, and also minimizes the number of TLB entries
|
||||
* needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
|
||||
* pressure is important; it may have a substantial impact on performance.
|
||||
*
|
||||
* If the firmware is compiled with static addresses, then @da should specify
|
||||
* the expected device address of this memory region. If @da is set to
|
||||
* FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then
|
||||
* overwrite @da with the dynamically allocated address.
|
||||
*
|
||||
* We will always use @da to negotiate the device addresses, even if it
|
||||
* isn't using an iommu. In that case, though, it will obviously contain
|
||||
* physical addresses.
|
||||
*
|
||||
* Some remote processors needs to know the allocated physical address
|
||||
* even if they do use an iommu. This is needed, e.g., if they control
|
||||
* hardware accelerators which access the physical memory directly (this
|
||||
* is the case with OMAP4 for instance). In that case, the host will
|
||||
* overwrite @pa with the dynamically allocated physical address.
|
||||
* Generally we don't want to expose physical addresses if we don't have to
|
||||
* (remote processors are generally _not_ trusted), so we might want to
|
||||
* change this to happen _only_ when explicitly required by the hardware.
|
||||
*
|
||||
* @flags is used to provide IOMMU protection flags, and @name should
|
||||
* (optionally) contain a human readable name of this carveout region
|
||||
* (mainly for debugging purposes).
|
||||
*/
|
||||
struct fw_rsc_carveout {
|
||||
uint32_t type;
|
||||
uint32_t da;
|
||||
uint32_t pa;
|
||||
uint32_t len;
|
||||
uint32_t flags;
|
||||
uint32_t reserved;
|
||||
uint8_t name[32];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fw_rsc_devmem - iommu mapping request
|
||||
* @type: type of resource
|
||||
* @da: device address
|
||||
* @pa: physical address
|
||||
* @len: length (in bytes)
|
||||
* @flags: iommu protection flags
|
||||
* @reserved: reserved (must be zero)
|
||||
* @name: human-readable name of the requested region to be mapped
|
||||
*
|
||||
* This resource entry requests the host to iommu map a physically contiguous
|
||||
* memory region. This is needed in case the remote processor requires
|
||||
* access to certain memory-based peripherals; _never_ use it to access
|
||||
* regular memory.
|
||||
*
|
||||
* This is obviously only needed if the remote processor is accessing memory
|
||||
* via an iommu.
|
||||
*
|
||||
* @da should specify the required device address, @pa should specify
|
||||
* the physical address we want to map, @len should specify the size of
|
||||
* the mapping and @flags is the IOMMU protection flags. As always, @name may
|
||||
* (optionally) contain a human readable name of this mapping (mainly for
|
||||
* debugging purposes).
|
||||
*
|
||||
* Note: at this point we just "trust" those devmem entries to contain valid
|
||||
* physical addresses, but this isn't safe and will be changed: eventually we
|
||||
* want remoteproc implementations to provide us ranges of physical addresses
|
||||
* the firmware is allowed to request, and not allow firmwares to request
|
||||
* access to physical addresses that are outside those ranges.
|
||||
*/
|
||||
struct fw_rsc_devmem {
|
||||
uint32_t type;
|
||||
uint32_t da;
|
||||
uint32_t pa;
|
||||
uint32_t len;
|
||||
uint32_t flags;
|
||||
uint32_t reserved;
|
||||
uint8_t name[32];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fw_rsc_trace - trace buffer declaration
|
||||
* @type: type of resource
|
||||
* @da: device address
|
||||
* @len: length (in bytes)
|
||||
* @reserved: reserved (must be zero)
|
||||
* @name: human-readable name of the trace buffer
|
||||
*
|
||||
* This resource entry provides the host information about a trace buffer
|
||||
* into which the remote processor will write log messages.
|
||||
*
|
||||
* @da specifies the device address of the buffer, @len specifies
|
||||
* its size, and @name may contain a human readable name of the trace buffer.
|
||||
*
|
||||
* After booting the remote processor, the trace buffers are exposed to the
|
||||
* user via debugfs entries (called trace0, trace1, etc..).
|
||||
*/
|
||||
struct fw_rsc_trace {
|
||||
uint32_t type;
|
||||
uint32_t da;
|
||||
uint32_t len;
|
||||
uint32_t reserved;
|
||||
uint8_t name[32];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fw_rsc_vdev_vring - vring descriptor entry
|
||||
* @da: device address
|
||||
* @align: the alignment between the consumer and producer parts of the vring
|
||||
* @num: num of buffers supported by this vring (must be power of two)
|
||||
* @notifyid is a unique rproc-wide notify index for this vring. This notify
|
||||
* index is used when kicking a remote processor, to let it know that this
|
||||
* vring is triggered.
|
||||
* @reserved: reserved (must be zero)
|
||||
*
|
||||
* This descriptor is not a resource entry by itself; it is part of the
|
||||
* vdev resource type (see below).
|
||||
*
|
||||
* Note that @da should either contain the device address where
|
||||
* the remote processor is expecting the vring, or indicate that
|
||||
* dynamically allocation of the vring's device address is supported.
|
||||
*/
|
||||
struct fw_rsc_vdev_vring {
|
||||
uint32_t da;
|
||||
uint32_t align;
|
||||
uint32_t num;
|
||||
uint32_t notifyid;
|
||||
uint32_t reserved;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fw_rsc_vdev - virtio device header
|
||||
* @type: type of resource
|
||||
* @id: virtio device id (as in virtio_ids.h)
|
||||
* @notifyid is a unique rproc-wide notify index for this vdev. This notify
|
||||
* index is used when kicking a remote processor, to let it know that the
|
||||
* status/features of this vdev have changes.
|
||||
* @dfeatures specifies the virtio device features supported by the firmware
|
||||
* @gfeatures is a place holder used by the host to write back the
|
||||
* negotiated features that are supported by both sides.
|
||||
* @config_len is the size of the virtio config space of this vdev. The config
|
||||
* space lies in the resource table immediate after this vdev header.
|
||||
* @status is a place holder where the host will indicate its virtio progress.
|
||||
* @num_of_vrings indicates how many vrings are described in this vdev header
|
||||
* @reserved: reserved (must be zero)
|
||||
* @vring is an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring'.
|
||||
*
|
||||
* This resource is a virtio device header: it provides information about
|
||||
* the vdev, and is then used by the host and its peer remote processors
|
||||
* to negotiate and share certain virtio properties.
|
||||
*
|
||||
* By providing this resource entry, the firmware essentially asks remoteproc
|
||||
* to statically allocate a vdev upon registration of the rproc (dynamic vdev
|
||||
* allocation is not yet supported).
|
||||
*
|
||||
* Note: unlike virtualization systems, the term 'host' here means
|
||||
* the Linux side which is running remoteproc to control the remote
|
||||
* processors. We use the name 'gfeatures' to comply with virtio's terms,
|
||||
* though there isn't really any virtualized guest OS here: it's the host
|
||||
* which is responsible for negotiating the final features.
|
||||
* Yeah, it's a bit confusing.
|
||||
*
|
||||
* Note: immediately following this structure is the virtio config space for
|
||||
* this vdev (which is specific to the vdev; for more info, read the virtio
|
||||
* spec). the size of the config space is specified by @config_len.
|
||||
*/
|
||||
struct fw_rsc_vdev {
|
||||
uint32_t type;
|
||||
uint32_t id;
|
||||
uint32_t notifyid;
|
||||
uint32_t dfeatures;
|
||||
uint32_t gfeatures;
|
||||
uint32_t config_len;
|
||||
uint8_t status;
|
||||
uint8_t num_of_vrings;
|
||||
uint8_t reserved[2];
|
||||
struct fw_rsc_vdev_vring vring[0];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fw_rsc_intmem - internal memory publishing request
|
||||
* @type: type of resource
|
||||
* @da: device address
|
||||
* @pa: physical address
|
||||
* @len: length (in bytes)
|
||||
* @reserved: reserved (must be zero)
|
||||
* @name: human-readable name of the region being published
|
||||
*
|
||||
* This resource entry allows a remote processor to publish an internal
|
||||
* memory region to the host. This resource type allows a remote processor
|
||||
* to publish the whole or just a portion of certain internal memories,
|
||||
* while it owns and manages any unpublished portion (eg: a shared L1
|
||||
* memory that can be split configured as RAM and/or cache). This is
|
||||
* primarily provided to allow a host to load code/data into internal
|
||||
* memories, the memory for which is neither allocated nor required to
|
||||
* be mapped into an iommu.
|
||||
*
|
||||
* @da should specify the required address as accessible by the device
|
||||
* without going through an iommu, @pa should specify the physical address
|
||||
* for the region as seen on the bus, @len should specify the size of the
|
||||
* memory region. As always, @name may (optionally) contain a human readable
|
||||
* name of this mapping (mainly for debugging purposes).
|
||||
*
|
||||
* Note: at this point we just "trust" these intmem entries to contain valid
|
||||
* physical bus addresses. these are not currently intended to be managed
|
||||
* as host-controlled heaps, as it is much better to do that from the remote
|
||||
* processor side.
|
||||
*/
|
||||
|
||||
struct fw_rsc_intmem {
|
||||
uint32_t type;
|
||||
uint32_t da;
|
||||
uint32_t pa;
|
||||
uint32_t len;
|
||||
uint32_t reserved[2];
|
||||
char name[32];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct fw_rsc_custom - used for custom resource types
|
||||
* @type: type of resource
|
||||
* @sub_type: type of custom resource
|
||||
* @rsc_size: size of @rsc (in bytes)
|
||||
* @rsc: the custom resource
|
||||
*
|
||||
* This resource allows for custom resources specific to an architecture or
|
||||
* device.
|
||||
*
|
||||
* @type is the generic CUSTOM type, @sub_type is the specific custom resource,
|
||||
* @rsc_size is the length of @rsc (in bytes), and @rsc is the actual
|
||||
* parameters. These will be interpreted by the host-side device-specific
|
||||
* driver.
|
||||
*/
|
||||
|
||||
struct fw_rsc_custom {
|
||||
uint32_t type;
|
||||
uint32_t sub_type;
|
||||
uint32_t rsc_size;
|
||||
union fw_custom rsc;
|
||||
};
|
||||
|
||||
#endif /* _RSC_TYPES_H_ */
|
|
@ -0,0 +1,18 @@
|
|||
/*
|
||||
* types.h - standard redefined types
|
||||
*/
|
||||
|
||||
#ifndef _TYPES_H_
|
||||
#define _TYPES_H_
|
||||
|
||||
typedef uint8_t __u8;
|
||||
typedef uint16_t __u16;
|
||||
typedef uint32_t __u32;
|
||||
typedef uint64_t __u64;
|
||||
|
||||
typedef uint8_t u8;
|
||||
typedef uint16_t u16;
|
||||
typedef uint32_t u32;
|
||||
typedef uint64_t u64;
|
||||
|
||||
#endif /* _TYPES_H_ */
|
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* File : pru_rpmsg.c
|
||||
*
|
||||
* Summary : An RPMsg implementation for the PRU to use while communicating
|
||||
* with the ARM host.
|
||||
*
|
||||
* Notes :
|
||||
* - Implementaion of the interface described in "pru_rpmsg.h"
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <pru_rpmsg.h>
|
||||
|
||||
struct pru_rpmsg_hdr {
|
||||
uint32_t src;
|
||||
uint32_t dst;
|
||||
uint32_t reserved;
|
||||
uint16_t len;
|
||||
uint16_t flags;
|
||||
uint8_t data[0];
|
||||
};
|
||||
|
||||
struct pru_rpmsg_ns_msg {
|
||||
char name[RPMSG_NAME_SIZE];
|
||||
char desc[RPMSG_NAME_SIZE];
|
||||
uint32_t addr;
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
int16_t pru_rpmsg_init(
|
||||
struct pru_rpmsg_transport *transport,
|
||||
struct fw_rsc_vdev_vring *vring0,
|
||||
struct fw_rsc_vdev_vring *vring1,
|
||||
uint32_t to_arm_event,
|
||||
uint32_t from_arm_event
|
||||
)
|
||||
{
|
||||
if (to_arm_event > MAX_VALID_EVENT || to_arm_event < MIN_VALID_EVENT)
|
||||
return PRU_RPMSG_INVALID_EVENT;
|
||||
|
||||
if (from_arm_event > MAX_VALID_EVENT || from_arm_event < MIN_VALID_EVENT)
|
||||
return PRU_RPMSG_INVALID_EVENT;
|
||||
|
||||
pru_virtqueue_init(&transport->virtqueue0, vring0, to_arm_event, from_arm_event);
|
||||
pru_virtqueue_init(&transport->virtqueue1, vring1, to_arm_event, from_arm_event);
|
||||
|
||||
return PRU_RPMSG_SUCCESS;
|
||||
}
|
||||
|
||||
int16_t pru_rpmsg_send(
|
||||
struct pru_rpmsg_transport *transport,
|
||||
uint32_t src,
|
||||
uint32_t dst,
|
||||
void *data,
|
||||
uint16_t len
|
||||
)
|
||||
{
|
||||
struct pru_rpmsg_hdr *msg;
|
||||
uint32_t msg_len;
|
||||
int16_t head;
|
||||
struct pru_virtqueue *virtqueue;
|
||||
|
||||
/*
|
||||
* The length of our payload is larger than the maximum RPMsg buffer size
|
||||
* allowed
|
||||
*/
|
||||
if (len > (RPMSG_BUF_SIZE - sizeof(struct pru_rpmsg_hdr)))
|
||||
return PRU_RPMSG_BUF_TOO_SMALL;
|
||||
|
||||
virtqueue = &transport->virtqueue0;
|
||||
|
||||
/* Get an available buffer */
|
||||
head = pru_virtqueue_get_avail_buf(virtqueue, (void **)&msg, &msg_len);
|
||||
|
||||
if (head < 0)
|
||||
return PRU_RPMSG_NO_BUF_AVAILABLE;
|
||||
|
||||
/* Copy local data buffer to the descriptor buffer address */
|
||||
memcpy(msg->data, data, len);
|
||||
msg->len = len;
|
||||
msg->dst = dst;
|
||||
msg->src = src;
|
||||
msg->flags = 0;
|
||||
msg->reserved = 0;
|
||||
|
||||
/* Add the used buffer */
|
||||
if (pru_virtqueue_add_used_buf(virtqueue, head, msg_len) < 0)
|
||||
return PRU_RPMSG_INVALID_HEAD;
|
||||
|
||||
/* Kick the ARM host */
|
||||
pru_virtqueue_kick(virtqueue);
|
||||
|
||||
return PRU_RPMSG_SUCCESS;
|
||||
}
|
||||
|
||||
int16_t pru_rpmsg_receive(
|
||||
struct pru_rpmsg_transport *transport,
|
||||
uint16_t *src,
|
||||
uint16_t *dst,
|
||||
void *data,
|
||||
uint16_t *len
|
||||
)
|
||||
{
|
||||
int16_t head;
|
||||
struct pru_rpmsg_hdr *msg;
|
||||
uint32_t msg_len;
|
||||
struct pru_virtqueue *virtqueue;
|
||||
|
||||
virtqueue = &transport->virtqueue1;
|
||||
|
||||
/* Get an available buffer */
|
||||
head = pru_virtqueue_get_avail_buf(virtqueue, (void **)&msg, &msg_len);
|
||||
|
||||
if (head < 0)
|
||||
return PRU_RPMSG_NO_BUF_AVAILABLE;
|
||||
|
||||
|
||||
/* Copy the message payload to the local data buffer provided */
|
||||
memcpy(data, msg->data, msg->len);
|
||||
*src = msg->src;
|
||||
*dst = msg->dst;
|
||||
*len = msg->len;
|
||||
|
||||
/* Add the used buffer */
|
||||
if (pru_virtqueue_add_used_buf(virtqueue, head, msg_len) < 0)
|
||||
return PRU_RPMSG_INVALID_HEAD;
|
||||
|
||||
/* Kick the ARM host */
|
||||
pru_virtqueue_kick(virtqueue);
|
||||
|
||||
return PRU_RPMSG_SUCCESS;
|
||||
}
|
||||
|
||||
int16_t pru_rpmsg_channel(
|
||||
enum pru_rpmsg_ns_flags flags,
|
||||
struct pru_rpmsg_transport *transport,
|
||||
char *name,
|
||||
char *desc,
|
||||
int32_t port
|
||||
)
|
||||
{
|
||||
struct pru_rpmsg_ns_msg ns_msg;
|
||||
uint8_t i;
|
||||
|
||||
for (i = 0; i < RPMSG_NAME_SIZE; i++) {
|
||||
ns_msg.name[i] = name[i];
|
||||
ns_msg.desc[i] = desc[i];
|
||||
}
|
||||
ns_msg.addr = port;
|
||||
ns_msg.flags = flags;
|
||||
|
||||
return pru_rpmsg_send(transport, port, 53, &ns_msg, sizeof(ns_msg));
|
||||
}
|
|
@ -0,0 +1,16 @@
|
|||
diff --git a/lib/pru_rpmsg/include/am335x/pru_iep.h b/lib/pru_rpmsg/include/am335x/pru_iep.h
|
||||
index d877ddd..064fb42 100644
|
||||
--- a/lib/pru_rpmsg/include/am335x/pru_iep.h
|
||||
+++ b/lib/pru_rpmsg/include/am335x/pru_iep.h
|
||||
@@ -251,6 +251,11 @@ typedef struct {
|
||||
|
||||
} pruIep;
|
||||
|
||||
+#ifdef __GNUC__
|
||||
+static volatile pruIntc *__CT_IEP = (void *)0x0002e000;
|
||||
+#define CT_IEP (*__CT_INTC)
|
||||
+#else
|
||||
volatile __far pruIep CT_IEP __attribute__((cregister("PRU_IEP", far), peripheral));
|
||||
+#endif
|
||||
|
||||
#endif /* _PRU_IEP_H_ */
|
|
@ -0,0 +1,149 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of Texas Instruments Incorporated nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/**
|
||||
* File : pru_virtqueue.c
|
||||
*
|
||||
* Summary : A virtual queue implementation to simplify vring usage.
|
||||
*
|
||||
* Notes :
|
||||
* - Implementaion of the interface described in "pru_virtqueue.h"
|
||||
*/
|
||||
#include <pru_virtqueue.h>
|
||||
|
||||
#ifndef __GNUC__
|
||||
volatile register uint32_t __R31;
|
||||
#else
|
||||
#include <pru/io.h>
|
||||
#endif
|
||||
|
||||
/* bit 5 is the valid strobe to generate system events with __R31 */
|
||||
#define INT_ENABLE (1 << 5)
|
||||
|
||||
/* __R31[3:0] can generate 15-0 which maps to system events 31-16
|
||||
* e.g. to generate PRU-ICSS System Event 17 (pru_mst_intr[1])
|
||||
* __R31 = (INT_ENABLE | (17 - INT_OFFSET));
|
||||
*/
|
||||
#define INT_OFFSET 16
|
||||
|
||||
void pru_virtqueue_init(
|
||||
struct pru_virtqueue *vq,
|
||||
struct fw_rsc_vdev_vring *vring,
|
||||
uint32_t to_arm_event,
|
||||
uint32_t from_arm_event
|
||||
)
|
||||
{
|
||||
vq->id = vring->notifyid;
|
||||
vq->to_arm_event = to_arm_event;
|
||||
vq->from_arm_event = from_arm_event;
|
||||
vq->last_avail_idx = 0;
|
||||
|
||||
vring_init(&vq->vring, vring->num, (void*)vring->da, vring->align);
|
||||
}
|
||||
|
||||
int16_t pru_virtqueue_get_avail_buf(
|
||||
struct pru_virtqueue *vq,
|
||||
void **buf,
|
||||
uint32_t *len
|
||||
)
|
||||
{
|
||||
int16_t head;
|
||||
struct vring_desc desc;
|
||||
struct vring_avail *avail;
|
||||
|
||||
avail = vq->vring.avail;
|
||||
|
||||
/* There's nothing available */
|
||||
if (vq->last_avail_idx == avail->idx)
|
||||
return PRU_VIRTQUEUE_NO_BUF_AVAILABLE;
|
||||
|
||||
/*
|
||||
* Grab the next descriptor number the ARM host is advertising, and
|
||||
* increment the last available index we've seen.
|
||||
*/
|
||||
head = avail->ring[vq->last_avail_idx++ & (vq->vring.num - 1)];
|
||||
|
||||
desc = vq->vring.desc[head];
|
||||
*buf = (void *)(uint32_t)desc.addr;
|
||||
*len = desc.len;
|
||||
|
||||
return (head);
|
||||
}
|
||||
|
||||
int16_t pru_virtqueue_add_used_buf(
|
||||
struct pru_virtqueue *vq,
|
||||
int16_t head,
|
||||
uint32_t len
|
||||
)
|
||||
{
|
||||
struct vring_used_elem *used_elem;
|
||||
uint32_t num;
|
||||
struct vring_used *used;
|
||||
|
||||
num = vq->vring.num;
|
||||
used = vq->vring.used;
|
||||
|
||||
if (head > (int)num)
|
||||
return PRU_VIRTQUEUE_INVALID_HEAD;
|
||||
|
||||
/*
|
||||
* The virtqueue's vring contains a ring of used buffers. Get a pointer to
|
||||
* the next entry in that used ring.
|
||||
*/
|
||||
used_elem = &used->ring[used->idx++ & (num - 1)];
|
||||
used_elem->id = head;
|
||||
used_elem->len = len;
|
||||
|
||||
return PRU_VIRTQUEUE_SUCCESS;
|
||||
}
|
||||
|
||||
int16_t pru_virtqueue_kick(
|
||||
struct pru_virtqueue *vq
|
||||
)
|
||||
{
|
||||
unsigned int r31;
|
||||
|
||||
/* If requested, do not kick the ARM host */
|
||||
if (vq->vring.avail->flags & VRING_AVAIL_F_NO_INTERRUPT)
|
||||
return PRU_VIRTQUEUE_NO_KICK;
|
||||
|
||||
/* Generate a system event to kick the ARM */
|
||||
r31 = (INT_ENABLE | (vq->to_arm_event - INT_OFFSET));
|
||||
#ifdef __GNUC__
|
||||
write_r31(r31);
|
||||
#else
|
||||
__R31 = r31;
|
||||
#endif
|
||||
|
||||
return PRU_VIRTQUEUE_SUCCESS;
|
||||
}
|
Loading…
Reference in New Issue