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lpc176x: Fix spi mode bits 

The lpc176x hardware spi initialization code was swapping the CPOL and
CPHA bits.  This caused the MAX31865 and MAX31856 chips to not work
correctly.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2020-07-10 13:41:13 -04:00
parent 5dc0c8aac0
commit c83688b7bc
1 changed files with 1 additions and 1 deletions
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2
src/lpc176x/spi.c
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@ -61,7 +61,7 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
uint32_t pclk = SystemCoreClock; uint32_t pclk = SystemCoreClock;
uint32_t div = DIV_ROUND_UP(pclk/2, rate) << 1; uint32_t div = DIV_ROUND_UP(pclk/2, rate) << 1;
res.cpsr = div < 2 ? 2 : (div > 254 ? 254 : div); res.cpsr = div < 2 ? 2 : (div > 254 ? 254 : div);
res.cr0 = 0x07 | (mode << 6); res.cr0 = 0x07 | ((mode & 2) << 5) | ((mode & 1) << 7);
return res; return res;
} }