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stm32f1: Wrap code to 80 columns 

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2019-02-27 14:14:30 -05:00
parent 796b7ac738
commit c3eb976119
3 changed files with 6 additions and 3 deletions
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3
src/stm32f1/adc.c
View File

@ -75,7 +75,8 @@ gpio_adc_sample(struct gpio_adc g)
/* ADC not busy, start conversion */ /* ADC not busy, start conversion */
if (!readb(&adc_busy)) { if (!readb(&adc_busy)) {
LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, g.bit); LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, g.bit);
LL_ADC_SetChannelSamplingTime(ADC1, g.bit, LL_ADC_SAMPLINGTIME_239CYCLES_5); LL_ADC_SetChannelSamplingTime(ADC1, g.bit
, LL_ADC_SAMPLINGTIME_239CYCLES_5);
LL_ADC_REG_StartConversionSWStart(ADC1); LL_ADC_REG_StartConversionSWStart(ADC1);
adc_busy = true; adc_busy = true;
adc_current_channel = g.bit; adc_current_channel = g.bit;

3
src/stm32f1/serial.c
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@ -17,7 +17,8 @@
void void
serial_init(void) serial_init(void)
{ {
const uint32_t pclk = __LL_RCC_CALC_PCLK2_FREQ(SystemCoreClock, LL_RCC_GetAPB2Prescaler()); const uint32_t pclk = __LL_RCC_CALC_PCLK2_FREQ(SystemCoreClock
, LL_RCC_GetAPB2Prescaler());
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);

3
src/stm32f1/spi.c
View File

@ -35,7 +35,8 @@ static void spi_set_mode(SPI_TypeDef *spi, uint8_t mode)
static void spi_set_baudrate(SPI_TypeDef *spi, uint32_t rate) static void spi_set_baudrate(SPI_TypeDef *spi, uint32_t rate)
{ {
const uint32_t pclk = __LL_RCC_CALC_PCLK1_FREQ(SystemCoreClock, LL_RCC_GetAPB1Prescaler()); const uint32_t pclk = __LL_RCC_CALC_PCLK1_FREQ(SystemCoreClock
, LL_RCC_GetAPB1Prescaler());
const uint32_t prescaler = pclk / rate; const uint32_t prescaler = pclk / rate;
uint32_t setting = LL_SPI_BAUDRATEPRESCALER_DIV256; uint32_t setting = LL_SPI_BAUDRATEPRESCALER_DIV256;