stm32: Simplify can.c irq handler
Don't perform any heavy tasks in the CAN interrupt handler - just notify a background task to handle anything pending. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
95adff7431
commit
bee544eaca
261
src/stm32/can.c
261
src/stm32/can.c
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@ -2,11 +2,13 @@
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//
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//
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// Copyright (C) 2019 Eug Krashtan <eug.krashtan@gmail.com>
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// Copyright (C) 2019 Eug Krashtan <eug.krashtan@gmail.com>
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// Copyright (C) 2020 Pontus Borg <glpontus@gmail.com>
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// Copyright (C) 2020 Pontus Borg <glpontus@gmail.com>
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// Copyright (C) 2021 Kevin O'Connor <kevin@koconnor.net>
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//
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <string.h> // memcpy
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#include <string.h> // memcpy
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#include "autoconf.h" // CONFIG_MACH_STM32F1
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#include "autoconf.h" // CONFIG_MACH_STM32F1
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#include "board/irq.h" // irq_disable
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#include "can.h" // SHORT_UUID_LEN
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#include "can.h" // SHORT_UUID_LEN
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#include "command.h" // DECL_CONSTANT_STR
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#include "command.h" // DECL_CONSTANT_STR
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#include "fasthash.h" // fasthash64
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#include "fasthash.h" // fasthash64
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@ -120,8 +122,7 @@ can_transmit_mbox(uint32_t id, int mbox, uint32_t dlc, uint8_t *pkt)
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mb->TIR = (id << CAN_TI0R_STID_Pos) | CAN_TI0R_TXRQ;
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mb->TIR = (id << CAN_TI0R_STID_Pos) | CAN_TI0R_TXRQ;
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}
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}
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// Blocking transmit function, it can race with the IRQ driven TX handler.
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// Blocking transmit function
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// This should(tm) not happen
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static void
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static void
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can_transmit(uint32_t id, uint32_t dlc, uint8_t *pkt)
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can_transmit(uint32_t id, uint32_t dlc, uint8_t *pkt)
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{
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{
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@ -142,58 +143,6 @@ pack_uuid(uint8_t *u)
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memcpy(u, &hash, SHORT_UUID_LEN);
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memcpy(u, &hash, SHORT_UUID_LEN);
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}
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}
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static void
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can_uuid_resp(void)
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{
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uint8_t short_uuid[SHORT_UUID_LEN];
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pack_uuid(short_uuid);
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can_transmit(PKT_ID_UUID_RESP, SHORT_UUID_LEN, short_uuid);
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}
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static void
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get_rx_data(uint8_t *buf, unsigned int mbox)
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{
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uint32_t rdlr = SOC_CAN->sFIFOMailBox[mbox].RDLR;
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buf[0] = (rdlr >> 0) & 0xff;
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buf[1] = (rdlr >> 8) & 0xff;
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buf[2] = (rdlr >> 16) & 0xff;
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buf[3] = (rdlr >> 24) & 0xff;
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uint32_t rdhr = SOC_CAN->sFIFOMailBox[mbox].RDHR;
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buf[4] = (rdhr >> 0) & 0xff;
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buf[5] = (rdhr >> 8) & 0xff;
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buf[6] = (rdhr >> 16) & 0xff;
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buf[7] = (rdhr >> 24) & 0xff;
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}
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// Return true if more data is available to send or mailboxes are full
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static int
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CAN_TxIrq(void)
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{
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int txdata = 1;
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// TODO: We need some kind of error handling?
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while (txdata) {
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int mbox = can_find_empty_tx_mbox();
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if (mbox < 0) {
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// All mboxes full, wait for next IRQ
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return 1;
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}
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int i;
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uint8_t databuf[8];
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for (i=0; i<8; i++) {
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if (serial_get_tx_byte(&(databuf[i])) == -1) {
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txdata = 0;
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break;
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}
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}
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if (i > 0) {
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can_transmit_mbox(MyCanId+1, mbox, i, databuf);
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}
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}
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return txdata;
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}
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#define CAN_FILTER_NUMBER 0
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#define CAN_FILTER_NUMBER 0
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static void
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static void
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@ -224,85 +173,144 @@ can_set_filter(uint32_t id1, uint32_t id2)
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}
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}
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static void
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static void
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CAN_RxCpltCallback(unsigned int mbox)
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can_process_data(uint32_t id, uint32_t dlc, uint8_t *data)
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{
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{
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CAN_FIFOMailBox_TypeDef *mb = &SOC_CAN->sFIFOMailBox[mbox];
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int i;
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uint32_t id = (mb->RIR >> CAN_RI0R_STID_Pos) & 0x7FF;
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for (i=0; i < dlc; i++)
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uint8_t dlc = mb->RDTR & CAN_RDT0R_DLC;
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serial_rx_byte(data[i]);
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uint8_t databuf[8];
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}
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if (!MyCanId) { // If serial not assigned yet
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static void
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if (id==PKT_ID_UUID && dlc == 0) {
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can_process_ping(uint32_t id, uint32_t dlc, uint8_t *data)
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// Just inform host about my UUID
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{
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can_uuid_resp();
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can_transmit(MyCanId+1, 0, NULL);
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} else if (id == PKT_ID_SET) {
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}
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uint8_t short_uuid[SHORT_UUID_LEN];
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pack_uuid(short_uuid);
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// compare my UUID with packet to check if this packet mine
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static void
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get_rx_data(databuf, mbox);
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can_process_reset(uint32_t id, uint32_t dlc, uint8_t *data)
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if (memcmp(&(databuf[2]), short_uuid, SHORT_UUID_LEN) == 0) {
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{
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MyCanId = databuf[0] | (databuf[1] << 8);
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uint32_t reset_id = data[0] | (data[1] << 8);
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can_set_filter(MyCanId, PKT_ID_UUID);
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if (reset_id == MyCanId)
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}
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NVIC_SystemReset();
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}
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}
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} else {
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if (id == MyCanId) {
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static void
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// compare my UUID with packet to check if this packet mine
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can_process_uuid(uint32_t id, uint32_t dlc, uint8_t *data)
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if (dlc == 0) {
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{
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// empty packet == ping request
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if (MyCanId)
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can_transmit(MyCanId+1, 0, NULL);
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return;
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} else {
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uint8_t short_uuid[SHORT_UUID_LEN];
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get_rx_data(databuf, mbox);
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pack_uuid(short_uuid);
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for (int i=0; i < dlc; i++) {
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can_transmit(PKT_ID_UUID_RESP, SHORT_UUID_LEN, short_uuid);
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serial_rx_byte(databuf[i]);
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}
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}
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}
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static void
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} else if (id == PKT_ID_UUID && dlc > 0) {
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can_process_set_id(uint32_t id, uint32_t dlc, uint8_t *data)
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get_rx_data(databuf, mbox);
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{
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if (memcmp(databuf, &MyCanId, 2) == 0) {
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uint8_t short_uuid[SHORT_UUID_LEN];
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// Reset from host
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pack_uuid(short_uuid);
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NVIC_SystemReset();
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}
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// compare my UUID with packet to check if this packet mine
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}
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if (memcmp(&data[2], short_uuid, SHORT_UUID_LEN) == 0) {
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MyCanId = data[0] | (data[1] << 8);
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can_set_filter(MyCanId, PKT_ID_UUID);
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}
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}
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}
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}
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static void
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can_process(uint32_t id, uint32_t dlc, uint8_t *data)
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{
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if (id == MyCanId) {
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if (dlc)
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can_process_data(id, dlc, data);
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else
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can_process_ping(id, dlc, data);
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} else if (id == PKT_ID_UUID) {
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if (dlc)
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can_process_reset(id, dlc, data);
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else
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can_process_uuid(id, dlc, data);
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} else if (id==PKT_ID_SET) {
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can_process_set_id(id, dlc, data);
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}
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}
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static struct task_wake canbus_wake;
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void
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can_dispatch_task(void)
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{
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if (!sched_check_wake(&canbus_wake))
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return;
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// Check for rx
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for (;;) {
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if (!(SOC_CAN->RF0R & CAN_RF0R_FMP0)) {
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// All rx mboxes empty, enable wake on rx IRQ
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irq_disable();
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SOC_CAN->IER |= CAN_IER_FMPIE0;
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irq_enable();
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break;
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}
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// Read and ack packet
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CAN_FIFOMailBox_TypeDef *mb = &SOC_CAN->sFIFOMailBox[0];
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uint32_t id = (mb->RIR >> CAN_RI0R_STID_Pos) & 0x7FF;
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uint32_t dlc = mb->RDTR & CAN_RDT0R_DLC;
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uint32_t rdlr = mb->RDLR, rdhr = mb->RDHR;
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SOC_CAN->RF0R = CAN_RF0R_RFOM0;
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// Process packet
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uint8_t data[8];
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data[0] = (rdlr >> 0) & 0xff;
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data[1] = (rdlr >> 8) & 0xff;
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data[2] = (rdlr >> 16) & 0xff;
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data[3] = (rdlr >> 24) & 0xff;
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data[4] = (rdhr >> 0) & 0xff;
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data[5] = (rdhr >> 8) & 0xff;
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data[6] = (rdhr >> 16) & 0xff;
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data[7] = (rdhr >> 24) & 0xff;
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can_process(id, dlc, data);
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}
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// Check for tx data
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for (;;) {
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int mbox = can_find_empty_tx_mbox();
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if (mbox < 0) {
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// All tx mboxes full, enable wake on tx IRQ
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irq_disable();
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SOC_CAN->IER |= CAN_IER_TMEIE;
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irq_enable();
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break;
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}
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int i;
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uint8_t databuf[8];
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for (i=0; i<8; i++) {
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if (serial_get_tx_byte(&(databuf[i])) == -1)
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break;
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}
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if (!i)
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break;
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can_transmit_mbox(MyCanId+1, mbox, i, databuf);
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}
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}
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DECL_TASK(can_dispatch_task);
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// This function handles CAN global interrupts
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// This function handles CAN global interrupts
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void
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void
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CAN_IRQHandler(void)
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CAN_IRQHandler(void)
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{
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{
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// RX
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if (SOC_CAN->RF0R & CAN_RF0R_FMP0) {
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if (SOC_CAN->RF0R & CAN_RF0R_FMP0) {
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// Mailbox 0
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// Rx
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while (SOC_CAN->RF0R & CAN_RF0R_FMP0) {
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SOC_CAN->IER &= ~CAN_IER_FMPIE0;
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CAN_RxCpltCallback(0);
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sched_wake_task(&canbus_wake);
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SOC_CAN->RF0R = CAN_RF0R_RFOM0;
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}
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}
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}
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if (SOC_CAN->RF1R & CAN_RF1R_FMP1) {
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uint32_t ier = SOC_CAN->IER;
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// Mailbox 1
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if (ier & CAN_IER_TMEIE
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while (SOC_CAN->RF1R & CAN_RF1R_FMP1) {
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&& SOC_CAN->TSR & (CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2)) {
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CAN_RxCpltCallback(1);
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// Tx
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SOC_CAN->RF1R = CAN_RF1R_RFOM1;
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SOC_CAN->IER &= ~CAN_IER_TMEIE;
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}
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sched_wake_task(&canbus_wake);
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}
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/* Check Overrun flag for FIFO0 */
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if (SOC_CAN->RF0R & CAN_RF0R_FOVR0) {
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/* Clear FIFO0 Overrun Flag */
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SOC_CAN->RF0R = CAN_RF0R_FOVR0;
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}
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/* Check Overrun flag for FIFO1 */
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if (SOC_CAN->RF1R & CAN_RF1R_FOVR1) {
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/* Clear FIFO1 Overrun Flag */
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SOC_CAN->RF1R = CAN_RF1R_FOVR1;
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}
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// TX
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if (SOC_CAN->IER & CAN_IER_TMEIE) { // TX IRQ enabled
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if (!CAN_TxIrq())
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SOC_CAN->IER = CAN_IER_FMPIE0 | CAN_IER_FMPIE1; // Disable TXIRQ
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}
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}
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}
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}
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@ -388,26 +396,21 @@ can_init(void)
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/*##-3- Configure Interrupts #################################*/
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/*##-3- Configure Interrupts #################################*/
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SOC_CAN->IER = CAN_IER_FMPIE0 | CAN_IER_FMPIE1; // RX mailbox IRQ
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SOC_CAN->IER = CAN_IER_FMPIE0; // RX mailbox IRQ
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armcm_enable_irq(CAN_IRQHandler, CAN_RX0_IRQn, 0);
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armcm_enable_irq(CAN_IRQHandler, CAN_RX0_IRQn, 0);
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if (CAN_RX0_IRQn != CAN_RX1_IRQn)
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if (CAN_RX0_IRQn != CAN_RX1_IRQn)
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armcm_enable_irq(CAN_IRQHandler, CAN_RX1_IRQn, 0);
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armcm_enable_irq(CAN_IRQHandler, CAN_RX1_IRQn, 0);
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if (CAN_RX0_IRQn != CAN_TX_IRQn)
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if (CAN_RX0_IRQn != CAN_TX_IRQn)
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armcm_enable_irq(CAN_IRQHandler, CAN_TX_IRQn, 0);
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armcm_enable_irq(CAN_IRQHandler, CAN_TX_IRQn, 0);
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// TODO: CAN_SCE_IRQ?n
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/*##-4- Say Hello #################################*/
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/*##-4- Say Hello #################################*/
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can_uuid_resp();
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can_process_uuid(0, 0, NULL);
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}
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}
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DECL_INIT(can_init);
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DECL_INIT(can_init);
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void
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void
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serial_enable_tx_irq(void)
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serial_enable_tx_irq(void)
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{
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{
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if (MyCanId == 0)
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sched_wake_task(&canbus_wake);
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// Serial port not initialized
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return;
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SOC_CAN->IER = CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | CAN_IER_TMEIE;
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}
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}
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